-- Modul Name : Standar Cell for D Flip-flop using Reset --

-- Purpose : To be used by SCMAP --

-- Author : Martadinata A --

-- Date : 14 November 2000 --

ENTITY dffres IS

PORT (

input : in bit;

clk : in bit;

reset : in bit;

output : out bit;

vdd : in bit;

vss : in bit

);

END dffres;

ARCHITECTURE VBE OF dffres IS

SIGNAL dffres_reg : REG_BIT REGISTER;

BEGIN

ASSERT ((vdd and not (vss)) = '1')

REPORT "power supply is missing on dffres"

SEVERITY WARNING;

dff : BLOCK ( ( clk AND NOT (clk'STABLE)) = '1' )

BEGIN

dffres_reg <= GUARDED '1' WHEN (reset = '1') else NOT input;

END BLOCK dff;

output <= NOT dffres_reg ;

END ;