head 1.1; branch 1.1.1; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.1 date 2005.04.23.00.39.14; author tak.sugawara; state Exp; branches 1.1.1.1; next ; commitid 1113426998c94567; 1.1.1.1 date 2005.04.23.00.39.14; author tak.sugawara; state Exp; branches; next ; commitid 1113426998c94567; desc @@ 1.1 log @Initial revision @ text @

3 Logic Synthesis

  First, I considered pipeline design using Stratix2 synthesis result.(Many Try and Errors).  After that Xilinx implementation has been done.Therefore Stratix2 implementation should give more optimal result than Xilinx.

Platform Result of Logic Synthesis Frequency Remarks
Xilinx Starter Kit(XC3S200 ISE7.1) 1918(99%) 25MHz AREA Priority First
Cyclone(EP1C12Q240C6Web Edition Quartus4.2SP1) 3624(30%) 104.7MHz SPEED Priority First
Stratix‡UiEP2S15F484C3
Web Edition Quartus4.2SP1)		 2926(23%) 165MHz SPEED Priority First


Spartan3




Cyclone


Stratix2



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