[oc] Modular FPGA board (PCI)

[Mr mike johnson <mikej@freeuk.com>]

Chaps, 

Just to make sure you're aware that Virtex-E devices are NOT 5V 
tolerant, and should therefore not be used in a 33Mhz 5V PCI slot. This 
may not be an issue in embedded apps, but
only Virtex (1) devices have the correct IO buffer for full spec 
compliance.

If you look at the pci mail list theres a bit more discussion about 
this. I have had my VHDL core running in real hardware for a while, but 
I am trying to make a generic 64/66Mhz core with a seperate wishbone 
backend. Timing is hard to meet in a non-E device !

Regards,
Mike.

John,

I too am working on a PCI card controlled by a FPGA. My main 
consideration (apart from price) is how many I/O pins are left over 
after 
the 50 pins (includes _INTA). Theres nothing worse than finding a board 

that suits your requirements except it doesn't have enough I/O pins. 
I've ordered a PCI prototyping board and a FPGA development board 
(Virtex-E) which I will 'glue' together and develop my PCI core. I have 
a 
copy of the PCI 2.2 specs and a pretty good book called "PCI BUS 
Demystified by Doug Abbott" so I'm just waiting for my boards to arrive.

My board will support full Initiator/Target functionality, probably 
will also 
support 66mhz (not 100mhz yet) but not 64bit (which should be easy 
enough to expand it to). Once my 'fudge board' works okay I'll get a 
board manufacturer to make me some alpha-test boards with the FPGA 
already mounted on them which will go out to my testers. Haven't 
enquired about the prices for manufacturing the boards yet so fingers 
crossed. The development platform & documentation costs are £260 
($400) which I think is quite for a PCI+FPGA development system. Sure 
beats the thousands of dollars some companies ask you for.

Paul McFeeters

----- Original Message ----- 
From: John Dalton <johnd@s... > 
To: cores@o...  
Date: Fri, 24 Nov 2000 14:12:43 +1100 
Subject: Re: [oc] Modular FPGA board 

> 
> 
> 
> > Are you working in the development of the free PCI core? 
> 
> No. 
> 
> > My idea was the opposite of your: I was planning to 
> > built a board for PCI testing only when the core will be 
> finished. 
> 
> My plan is for the PCI hardware to be an FPGA connected directly 
> to a PCI connector.  There would also be a bunch of pins going off 
> to the 
> main FPGA.  The only questions are: 
> 1) How big an FPGA do you need, and 
> 2) How many pins do you need to communicate with the main FPGA? 
> 
> An answer to question 1) is not too important, as within a 
> family it is possible to get different sized FPGAs with a common 
> footprint. 
> 
> In a way, I think it is a good thing to design the PCI core and the 
> hardware 
> at the same time.  This forces the hardware and core to be 
> independent, 
> leading to maximum portability for the core and maximum versatility 
> for the hardware. 
> 
> > If a PCI core is validated through simulations and it doesn't 
> work over a 
> > specific board, what should I do to detect the problem? 
> Measurements using 
> > oscilloscopes and logical analysers are not possible, because 
> they modify 
> > the circuit when connected into them due to cable impedances, 
> that 
> > generates multiple reflection. Is there any solution? 
> 
> Since we are using programmable logic, it should be possible to use 
> the system 
> to validate itself.  Simply program a logic analyser into the FPGA. 
> One of the initial applications of the Pamette (an FPGA board built 
> bt Digital) was to verify the operation of a PCI bus to which it 
> was 
> connected. 
> 
> > I don't think that an FPGA for PCI have to fit in a socket. 
> IMHO, it has 
> > to be soldered in a board. And if this board should fit in a 
> SIMM socket, 
> > the FPGA has to be a TQFP or BGA packet. 
> 
> Agree.  My current thinking is to build the PCI as a separate 
> board, 
> with a chip soldered directly to it.  PCI tracks would go directly 
> to 
> a PCI connector.  The main logic board and PCI board would be 
> plugged into each other.  Unfortunately I don't think a SIMM socket 
> is possible due to mechanical constraints. 
> 
> > TO DO AT HOME??? Well, if I understood it right, it is much 
> harder to do 
> > the copper lines for the FPGA than for the edge connector. 
> 
> Yep.  Do at home.  I'm proposing to use CAD (ideally gpcb, but I 
> don't 
> think it is finished) to layout a board, printing it 1:1 then using 
> optical 
> means (Riston?) to transfer the design to a PCB.  With careful 
> construction 
> it *might* be possible to do a board for a chip with 0.5mm pins at 
> home. 
> In my experience, aligning two sides of a board, to a fraction of a 
> mm, is 
> difficult to do at home.  Hence it is difficult to do a double 
> sided 
> edge connector.  (Single sided is okay.) 
> 
> Of course this does not rule out the convenience of paying someone 
> to build the board for you.  But it would be nice to cater for all 
> tastes. 
> 
> > Is there any 
> > problem if the lines of the edge connector have the right 
> distance and 
> > smaller width (ie, increasing the spacing)? 
> 
> Probably not a good idea.  Edge connector widths and spacings have 
> generally been designed to maximise chances of a good connection 
> while minimising chances of a short between contacts.  Changing 
> widths could impact reliability. 
> 
> > Greetings from Brazil! 
> 
> G'day from Australia. 
> 
> John 
> 
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