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[cvs-checkins] ethernet/bench/verilog tb_eth_top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/bench/verilog tb_eth_top.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Wed, 15 Aug 2001 16:04:30 +0200
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	01/08/15 16:04:30

Modified files:
	bench/verilog  : tb_eth_top.v 

Log message:
	Signal names changed on the top level for easier pad insertion (ASIC).

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