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[cvs-checkins] or1k/mp3/rtl/verilog/or1200 or1200_cpu.v or120 ...

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	02/01/18 08:56:06

Modified files:
	mp3/rtl/verilog/or1200: or1200_cpu.v or1200_defines.v 
	                        or1200_du.v or1200_except.v 
	                        or1200_genpc.v or1200_lsu.v or1200_pic.v 
	                        or1200_sprs.v or1200_top.v 

Log message:
	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.

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