[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] can/ ench/verilog/can_testbench.v tl/verilog/c ...

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/02/09 17:40:31

Modified files:
	bench/verilog  : can_testbench.v 
	rtl/verilog    : can_acf.v can_bsp.v can_btl.v can_top.v 
	sim/rtl_sim/run: wave.do 

Log message:
	Overload fixed. Hard synchronization also enabled at the last bit of
	interframe.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml