[cvs-checkins] mem_if/ ench/verilog/mem_if_bench.v ench/veril ...

[OpenCores CVS Agent <cvs@www.opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	mem_if
Changes by:	mihad	03/07/24 13:27:39

Modified files:
	bench/verilog  : mem_if_bench.v mem_if_bench_defines.v 
	                 wb_bus_mon.v wb_master32.v wb_model_defines.v 
	rtl/verilog    : mem_if_flash_if.v mem_if_registered_feedback.v 
	sim/rtl_sim/run: debug.do run_sim.scr 

Log message:
	Added WISHBONE revision B3 support.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml