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Re: [fpu] Add/Sub Unit Test Vectors



Hi,

--- Rudolf Usselmann <rudi@inet.co.th> wrote:

> > As I see the interface has:
> > 1. signals for INF and NaN but teh core does not
> > encode them to the output, So do you suggest to
> > generate these special values in a seperate block.
> 
> The INF and NAN are OUTPUTS. They are asserted when
> one of the input
> operands was a NAN or INF. Currently I don not
> enforce that a INF or NAN
> values is correctly represented on the sum output.
> Should I add this ?
> I thought it will be mostly used to generate an
> exception ....

As far as I know that these special values must appear
on FPU registers and not signals or exceptions only. 

> 
> > 2. Denormailized numbers are used as outputs so an
> > external block will do the normalization??
> 
> Please explain how you came to that conclusion ?!
> 
> I thought I designed it so that the output IS
> normalized ?!
> Meaning the leading 1 is hidden and the exponent is
> adjusted ...
> 
> As far as I know, the output is normalized - unless
> you found a bug ...
> 
> > 3. Do your core accept denormalized numbers? it
> should
> > do.
> 
> It has been designed to work with Normalized
> numbers. I'm not sure what
> it will actually do if a denormalized number is
> presented.

But as I know from the IEEE std the denormalized
numbers are so important in some calculations. I am
not sure why but I'll give you examples tomorrow. but
it should be supported for both inputs and outputs

> 
> > 4. How do you handel NAN and INF numbers at the
> input?
> 
> Assert INF and/or NAN output signal.


Note: denormalized numbers aer no. that have  exp=0
and fract!=0

I think the issues of normalizations, special values
and exceptions should be handeled globally or the
cores will generate and use different values and that
will reflect incorrect no. on the registers.

what I am not sure about it is should we have an
instruction to normalize denormalized numbers??

I am going to write a summary of what I know of IEEE
std.

Regards
Jamil Khatib

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