RE: [fpu] Add/sub test

["Rudolf Usselmann" <russelmann@hotmail.com>]

>From: owner-fpu@opencores.org [mailto:owner-fpu@opencores.org]On Behalf
>Of Jamil Khatib
>
>
>Hi all,
>
>I need to design the test bench/ or C code to test the
>adder circuit.
>
>These are my suggested Tests to be run on the add/sub
>unit

You see this, is exactly the problem with you and your specifying.
I have already written such a program and a test bench 3 weeks ago.
I attached my program, there is not a lot of documentations and some
features might be missing, but it works and generates test code.
It has only been tested under NT.

rudi



HINTS
=====
(verilog)

reg	[107:0]	tmem[0:200000];

$readmemh ("fasu_test/fasu_rand_sm.hex", tmem);

tmp = tmem[i];
exc = tmp[107:100];  // exceptions TBD
oper = tmp[99:96];   // operation 1=add, 2=sub, 4=mul, 8=div
opa = tmp[95:64];    // operand a
opb = tmp[63:32];    // operand b
exp = tmp[31:00];    // result

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