[openrisc] or1ksim

["Damjan Lampret" <lampret@opencores.org>]

Chris,

some hints about or1ksim.

What is not implemented:
- power management
- debug unit
- performance counters
- programmable interrupt controller

Needs revision:
- instructions (historically or1ksim was designed before we had assembler
therefore all instructions are disassembled on the fly and interpreted - I'd
say it would be possible to increase simulation speed if this would be
changed - however this is just optimization)
- MMU (they are implemented according to old architecture - SPRs need to be
updated)
- caches (they are infact implemented such that they don't provide data
directly to instruction or load/store unit but rather just for gathering
cache statistis - cache management SPRs are not implemented)
- exceptions (some exceptions like range, alignment are not implemented)

Also it would be possible to implement peripherals. 16450 is implemented for
example.

Marko managed to build gdb for or1k today (but it isn't finish, just it
built w/o problems). One task would also be to interface or1ksim to gdb.
This is very important for software people that would like to port software
for or1k using or1ksim and they gdb (or some gdb front-end) for debugging.

regards,
Damjan

PS Try to run three examples in or1ks/testbench (see testbench/README for
details).