[openrisc] vector/floating point regs

["Marko Mlinar" <markom@opencores.org>]

Hi!

With Damjan we were discussing that having extra register file for floating
point is maybe
too much, since or1k architecture targets applications, for which power and
size is more
important than speed. In our case even speed would increase, e.g.:
l.lwz r18,0(r1)
l.itof vf1,r18
...
l.ftoi r18,vf1
l.sw 0(r1),r18

would be replaced by more simpler:
l.lwz r18,0(r1)
...
l.sw 0(r1),r18

So, if there are no objections, we would move all accesses to GPRs.
Everything else stays the same, and there is no need for instructions like:
l.itof.s; l.ftoi.s; l.itof.d; l.ftoi.d.

32/64 bit issues would also need to be handled -- IMHO critical only
when combining 32bit and double precision; special instructions can
be added, if such (rare?) application exists.

Marko


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