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Re: Re: [openrisc] OR1200 problem

To: openrisc@opencores.org
Subject: Re: Re: [openrisc] OR1200 problem
From: Damjan Lampret <lampret@opencores.org>
Date: Wed, 24 Apr 2002 07:55:20 CET
In-Reply-To: <3CC60AE4.5040406@aeste.net>
Reply-To: openrisc@opencores.org
Sender: owner-openrisc@opencores.org

OR1200 is being tested with the Cadence NCsim. What kind of simulator do you use?

If it is something from Cadence, Mentor or Synopsys, it should probably work. Check that you have applied all the latest bug fixes to the simulator...

regards,
Damjan

> 
> I think that it might be a simulator problem.. because I've got another
> issue with another core.. for the memory controller core, the RTL works
> fine, but the synthesized netlist doesn't.. (:
> 
> I don't think that it's a real problem.. I'll take whatever works for now..
> 

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- Re: [openrisc] OR1200 problem
  - From: Shawn Tan <shawn.tan@aeste.net>

References:
- Re: [openrisc] OR1200 problem
  - From: Shawn Tan <shawn.tan@aeste.net>

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