[openrisc] DC query.

[Christian Melki <christian.melki@axis.com>]

Hello ppl.

Thought perhaps somebody could help me
with this trivial question.. im running an evaluation
version of DC ( not ultra.. unfortunately.. see if i can get one
ultra eval later.. ). But im getting this error message in the
logs.. And since i find the dc_shell very annoying without auto-
completion.. ( perhaps a feature that one can turn on.. )?
The WORK name directory path sound very much like VHDL-style
to me..

Anyway.. here is the log.. any ideas?
Information: Building the design 'or1200_wb_biu'. (HDL-193)
Warning: Can't find the design 'or1200_wb_biu'
        in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference w'or1200_wb_biu' in 'or1200_top'.
(LINK-5)
Information: Building the design 'or1200_immu_top'. (HDL-193)
Warning: Can't find the design 'or1200_immu_top'
        in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'or1200_immu_top' in 'or1200_top'.
(LINK-5)
... and so on.

Btw. the or1200 did reach 200MHz in an unnamed .13 target without
any beating on the design.. But that was with Cadence BG.. and now im
trying to play a bit with Synopsys DC.. 200MHz WC in .13 was easy.

regards,
Christian Melki

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