RE: [openrisc] Running slower wishone interfaces

["Michael Scott" <mike.scott@jennic.com>]

Hi Damjan,
         Did you have any success running slower wishbone interfaces
with modelsim 5.6 ?

For the moment I'm up & running with a system with wishbone/RISC clock ratio
of 1:1


Regards,

Mike



-----Original Message-----
From: owner-openrisc@opencores.org
[mailto:owner-openrisc@opencores.org]On Behalf Of Damjan Lampret
Sent: 01 April 2003 23:08
To: openrisc@opencores.org
Subject: Re: [openrisc] Running slower wishone interfaces


Mike,

I'm going to have a closer look at this at the end of this week, I'm also
going to try with Modelsim.

regards,
Damjan

----- Original Message -----
From: "Michael Scott" <mike.scott@jennic.com>
To: <openrisc@opencores.org>
Sent: Monday, March 31, 2003 2:37 AM
Subject: [openrisc] Running slower wishone interfaces


> Hi All,
>       I've just managed to get the OpenRISC core running under Modelsim
5.6.
> However
> It only seems to work with the Risc clock & Wishbone clock running at 1:1
> I've tried changing the appropriate defines and the clmode input for 1:2
and
> 1:4 ratios
> but the instruction address doesn't appear increment correctly. Instead of
> fetching
> from 0x100, 0x104, 0x0108  it follows 0x100, 0x108, 0x110
> This looks suspiciously like a clock domain issue and a missing
synchroniser
> somewhere but
> I've checked the code & defines and it seems ok
>
> Has anybody successfully run the core under modelsim with slower
> (half/quarter speed)
> wishbone interfaces on instruction/data memories ?
>
>
> Regards,
>
> Mike Scott
>
> ___________________________________________________
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
> www.jennic.com  Tel: +44 (0) 114 2812655   Confidential
> ___________________________________________________
>
>
>
>

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