[pci] reviera - compile script

[pinhas.krengel@formalized.com]

Attached is a script to compile the design.
Three scripts are available:
1. set environmet of aldec (optional)
2. batch file to start the compiler
3. do file

1.
winset LM_LICENSE_FILE =  
winset MODEL_TECH      =
winset PATH=C:\WINDOWS;C:\WINDOWS\COMMAND;

winset VSIMSALIBRARYCFG=C:\Program Files\Aldec\Riviera\vlib
winset PATH=%PATH%;C:\Program Files\Aldec\Riviera\bin

2.
echo start > rx_cmp1.txt
del rv_cmp.log
copy ..\rtl\pci_constants.v      ..\bench\pci_constants.v
copy ..\rtl\pci_user_constants.v ..\bench\pci_user_constants.v
copy ..\rtl\bus_commands.v       ..\bench\bus_commands.v
copy ..\rtl\timescale.v          ..\bench\timescale.v

call "C:\Program Files\Aldec\Riviera\etc\setenv.bat"

"C:\Program Files\Aldec\Riviera\bin\vsimsa.exe" rv_cmp.do

echo start > rx_cmp2.txt

3. 
cd C:\pini\verilog\OpenCore\pci\rv

log rv_cmp.log

alib rwork rwork.lib
set rwork  rwork.lib

alog -all -dbg -work rwork "C:\Program Files\modelsimXE\xilinx\verilog\src\unisims\RAMB4_S16_S16.v" "C:\Program Files\modelsimXE\xilinx\verilog\src\glbl.v" ..\rtl\pci_parity_check.v ..\rtl\pci_target_unit.v ..\rtl\wb_addr_mux.v ..\rtl\cbe_en_crit.v ..\rtl\fifo_control.v ..\rtl\out_reg.v ..\rtl\pci_tpram.v ..\rtl\wb_master.v ..\rtl\conf_cyc_addr_dec.v ..\rtl\frame_crit.v ..\rtl\pci_target32_clk_en.v ..\rtl\pciw_fifo_control.v ..\rtl\wb_slave.v ..\rtl\conf_space.v ..\rtl\frame_en_crit.v ..\rtl\par_crit.v ..\rtl\pciw_pcir_fifos.v ..\rtl\wb_slave_unit.v ..\rtl\frame_load_crit.v ..\rtl\pci_bridge32.v ..\rtl\pci_target32_devs_crit.v ..\rtl\perr_crit.v ..\rtl\wbr_fifo_control.v ..\rtl\cur_out_reg.v ..\rtl\pci_decoder.v ..\rtl\pci_target32_interface.v ..\rtl\perr_en_crit.v ..\rtl\wbw_fifo_control.v ..\rtl\decoder.v ..\rtl\pci_in_reg.v ..\rtl\serr_crit.v ..\rtl\wbw_wbr_fifos.v ..\rtl\delayed_sync.v ..\rtl\irdy_out_crit.v ..\rtl\pci_io_mux.v ..\rtl\pci_io_mux_ad_en_crit.v ..\rtl\pci_io_mux_ad_load_crit.v ..\rtl\pci_target32_sm.v ..\rtl\serr_en_crit.v ..\rtl\delayed_write_reg.v ..\rtl\mas_ad_en_crit.v ..\rtl\mas_ad_load_crit.v ..\rtl\pci_master32_sm.v ..\rtl\pci_target32_stop_crit.v ..\rtl\synchronizer_flop.v ..\rtl\async_reset_flop.v ..\rtl\mas_ch_state_crit.v ..\rtl\pci_master32_sm_if.v ..\rtl\pci_target32_trdy_crit.v ..\rtl\top.v ..\rtl\pci_rst_int.v ..\rtl\sync_module.v ..\rtl\wb_tpram.v ..\bench\pci_blue_arbiter.v ..\bench\pci_bus_monitor.v ..\bench\pci_behaviorial_device.v ..\bench\pci_behaviorial_master.v ..\bench\pci_behaviorial_target.v ..\bench\wb_slave_behavioral.v ..\bench\wb_bus_mon.v +define+RV ..\bench\pci_behavioral_iack_target.v ..\bench\pci_unsupported_commands_master.v ..\bench\wb_master32.v ..\bench\wb_master_behavioral.v ..\bench\system.v




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Best Regards,

Pinhas Krengel
Sr. ASIC / FPGA Engineer
Formalized Design Alliance Partner
011 972-9-894-7865 Home Office
011 972-54-679-119 Portable
480-545-4555 Jim McHood, VP Engineering
www.formalized.com

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