Re: [usb] some question about the code of the USB function core

[Rudolf Usselmann <rudi@asics.ws>]

On Sunday 31 March 2002 07:14 pm, you wrote:
> Hi, rudi:
>
...
> >How about writing a test bench ???
>
>    Exactly I don't know how to write a good and full coverage testbench
> now. That skill is what I want to learn. Can someone help me about that?
> Any advice and papers are welcomed. Maybe I can have a try.   :)

Take a look at :
http://janick.bergeron.com/default.htm

....
> >
> >No this does not bring rtl closer to gate level simulations. Timing
> >will always differ depending on your technology. The "#1" is really
> >absolutely meaningless. The only reason I like to add them is
> >because it makes debugging of rtl so much easier.
>
> Why did the delay in the code make debugging much easier ?
> I don't understand what do you mean exactly. Could you explain that more
> ? Thanks.

Because all Flip Flop outputs change one time unit after the
rising clock edge (synchronous that is, async set/reset still
can change at any time). I find it easier to follow signals this
way. It's a personal preference thing. You can write a perl
script to remove all "#1" and it should still work ...

rudi


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