Timing Multi Corner Report Min Delay Analysis

SmartTime Version 2022.1.0.10

Microsemi Corporation - Microsemi Libero Software Release v2022.1 (Version 2022.1.0.10)

Date: Mon Jul 18 09:52:17 2022

Design ctu_can_fd_libero_top
Family PolarFire
Die MPF300TS
Package FCG1152
Temperature Range -40 - 100 C
Voltage Range 0.97 - 1.03 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions slow_lv_ht, slow_lv_lt, fast_hv_lt

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
SYS_CLK 10.000 100.000 0.077 fast_hv_lt

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain SYS_CLK

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) Operating Conditions
Path 1 can_top_level_inst/tx_arbitrator_inst/tran_frame_type_dbl_buf:CLK can_top_level_inst/tx_arbitrator_inst/tran_frame_type_com:D 0.152 0.077 2.238 2.161 0.069 fast_hv_lt
Path 2 can_top_level_inst/tx_arbitrator_inst/tran_dlc_dbl_buf[1]:CLK can_top_level_inst/tx_arbitrator_inst/tran_dlc_com[1]:D 0.153 0.078 2.239 2.161 0.069 fast_hv_lt
Path 3 can_top_level_inst/can_core_inst/protocol_control_inst/rx_shift_reg_inst/shift_reg_byte_inst/byte_shift_reg_gen.0.shift_reg_proc.shift_reg_q_3[4]:CLK can_top_level_inst/can_core_inst/protocol_control_inst/rx_shift_reg_inst/shift_reg_byte_inst/byte_shift_reg_gen.0.shift_reg_proc.shift_reg_q_3[5]:D 0.146 0.078 2.239 2.161 0.062 fast_hv_lt
Path 4 can_top_level_inst/can_core_inst/protocol_control_inst/rx_shift_reg_inst/shift_reg_byte_inst/byte_shift_reg_gen.0.shift_reg_proc.shift_reg_q_3[0]:CLK can_top_level_inst/can_core_inst/protocol_control_inst/rx_shift_reg_inst/shift_reg_byte_inst/byte_shift_reg_gen.0.shift_reg_proc.shift_reg_q_3[1]:D 0.146 0.078 2.219 2.141 0.062 fast_hv_lt
Path 5 can_top_level_inst/can_core_inst/protocol_control_inst/rx_shift_reg_inst/shift_reg_byte_inst/byte_shift_reg_gen.0.shift_reg_proc.shift_reg_q_3[5]:CLK can_top_level_inst/can_core_inst/protocol_control_inst/rx_shift_reg_inst/shift_reg_byte_inst/byte_shift_reg_gen.0.shift_reg_proc.shift_reg_q_3[6]:D 0.152 0.080 2.245 2.165 0.066 fast_hv_lt

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: can_top_level_inst/tx_arbitrator_inst/tran_frame_type_dbl_buf:CLK
To: can_top_level_inst/tx_arbitrator_inst/tran_frame_type_com:D
data arrival time 2.238
data required time - 2.161
slack 0.077
Data arrival time calculation
SYS_CLK 0.000 0.000
clk_sys Clock source + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.795 0.795 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.262 1.057 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.087 1.144 1 r
I_1:A net clk_sys_ibuf_Z + 0.223 1.367 r
I_1:Y cell ADLIB:GB + 0.113 1.480 9 r
I_1/U0_RGB1_RGB4:A net I_1/U0_Y + 0.252 1.732 r
I_1/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.038 1.770 2055 f
can_top_level_inst/tx_arbitrator_inst/tran_frame_type_dbl_buf:CLK net I_1/U0_RGB1_RGB4_rgb_net_1 + 0.316 2.086 r
can_top_level_inst/tx_arbitrator_inst/tran_frame_type_dbl_buf:Q cell ADLIB:SLE + 0.082 2.168 1 f
can_top_level_inst/tx_arbitrator_inst/tran_frame_type_com:D net can_top_level_inst/tx_arbitrator_inst/tran_frame_type_dbl_buf_Z + 0.070 2.238 f
data arrival time 2.238
Data required time calculation
SYS_CLK Clock Constraint 0.000 0.000
clk_sys Clock source + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.915 0.915 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.288 1.203 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.100 1.303 1 r
I_1:A net clk_sys_ibuf_Z + 0.244 1.547 r
I_1:Y cell ADLIB:GB + 0.124 1.671 9 r
I_1/U0_RGB1_RGB4:A net I_1/U0_Y + 0.278 1.949 r
I_1/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.043 1.992 2055 f
can_top_level_inst/tx_arbitrator_inst/tran_frame_type_com:CLK net I_1/U0_RGB1_RGB4_rgb_net_1 + 0.357 2.349 r
clock reconvergence pessimism + -0.257 2.092
can_top_level_inst/tx_arbitrator_inst/tran_frame_type_com:D Library hold time ADLIB:SLE + 0.069 2.161
data required time 2.161
Operating Conditions fast_hv_lt

SET External Hold

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Hold (ns) External Hold (ns) Operating Conditions
Path 1 data_in[6] can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[6]:D 1.736 1.736 0.111 1.933 slow_lv_ht
Path 2 data_in[6] can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_12[6]:D 1.816 1.816 0.111 1.853 slow_lv_ht
Path 3 data_in[6] can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_6[6]:D 1.993 1.993 0.111 1.679 slow_lv_ht
Path 4 data_in[11] can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_5[11]:D 2.021 2.021 0.111 1.674 slow_lv_ht
Path 5 data_in[6] can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_10[6]:D 2.011 2.011 0.111 1.660 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: data_in[6]
To: can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[6]:D
data arrival time 1.736
data required time - N/C
slack N/C
Data arrival time calculation
data_in[6] 0.000 0.000 r
data_in_ibuf[6]/U_IOPAD:PAD net data_in[6] + 0.000 0.000 r
data_in_ibuf[6]/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.528 0.528 1 r
data_in_ibuf[6]/U_IOIN:YIN net data_in_ibuf[6]/YIN + 0.000 0.528 r
data_in_ibuf[6]/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.302 0.830 29 r
can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/port_a_data_in_i[6]:A net data_in_c[6] + 0.810 1.640 r
can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/port_a_data_in_i[6]:Y cell ADLIB:CFG3 + 0.074 1.714 21 r
can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[6]:D net can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/port_a_data_in_i_Z[6] + 0.022 1.736 r
data arrival time 1.736
Data required time calculation
SYS_CLK N/C N/C
clk_sys Clock source + 0.000 N/C r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 N/C r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.322 N/C 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.471 N/C r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.150 N/C 1 r
I_1:A net clk_sys_ibuf_Z + 0.383 N/C r
I_1:Y cell ADLIB:GB + 0.167 N/C 9 r
I_1/U0_RGB1_RGB0:A net I_1/U0_Y + 0.424 N/C r
I_1/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.059 N/C 1943 f
can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[6]:CLK net I_1/U0_RGB1_RGB0_rgb_net_1 + 0.582 N/C r
can_top_level_inst/txt_buf_comp_gen.4.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[6]:D Library hold time ADLIB:SLE + 0.111 N/C
Operating Conditions slow_lv_ht

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/data_mux_control_registers_comp/data_out[21]:CLK data_out[21] 2.495 4.584 4.584 fast_hv_lt
Path 2 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/data_mux_control_registers_comp/data_out[20]:CLK data_out[20] 2.535 4.624 4.624 fast_hv_lt
Path 3 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/data_mux_control_registers_comp/data_out[27]:CLK data_out[27] 2.560 4.651 4.651 fast_hv_lt
Path 4 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/data_mux_control_registers_comp/data_out[22]:CLK data_out[22] 2.608 4.696 4.696 fast_hv_lt
Path 5 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/settings_reg_comp/reg_value_r[6]:CLK can_tx 2.599 4.698 4.698 fast_hv_lt

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/data_mux_control_registers_comp/data_out[21]:CLK
To: data_out[21]
data arrival time 4.584
data required time - N/C
slack N/C
Data arrival time calculation
SYS_CLK 0.000 0.000
clk_sys Clock source + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.795 0.795 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.262 1.057 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.087 1.144 1 r
I_1:A net clk_sys_ibuf_Z + 0.223 1.367 r
I_1:Y cell ADLIB:GB + 0.113 1.480 9 r
I_1/U0_RGB1_RGB2:A net I_1/U0_Y + 0.255 1.735 r
I_1/U0_RGB1_RGB2:Y cell ADLIB:RGB + 0.038 1.773 2240 f
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/data_mux_control_registers_comp/data_out[21]:CLK net I_1/U0_RGB1_RGB2_rgb_net_1 + 0.316 2.089 r
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/data_mux_control_registers_comp/data_out[21]:Q cell ADLIB:SLE + 0.082 2.171 1 f
can_top_level_inst/memory_registers_inst/data_out_cZ[21]:C net can_top_level_inst/memory_registers_inst/control_registers_rdata[21] + 0.080 2.251 f
can_top_level_inst/memory_registers_inst/data_out_cZ[21]:Y cell ADLIB:CFG4 + 0.083 2.334 1 f
data_out_obuf[21]/U_IOTRI:D net data_out_c[21] + 0.620 2.954 f
data_out_obuf[21]/U_IOTRI:DOUT cell ADLIB:IOTRI_OB_EB + 0.295 3.249 1 f
data_out_obuf[21]/U_IOPAD:D net data_out_obuf[21]/DOUT + 0.000 3.249 f
data_out_obuf[21]/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 1.335 4.584 0 f
data_out[21] net data_out[21] + 0.000 4.584 f
data arrival time 4.584
Data required time calculation
SYS_CLK N/C N/C
clk_sys Clock source + 0.000 N/C r
data_out[21] N/C f
Operating Conditions fast_hv_lt

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Removal (ns) Skew (ns) Operating Conditions
Path 1 can_top_level_inst/rst_sync_inst/rst:CLK can_top_level_inst/memory_registers_inst/test_registers_cs_reg:ALn 0.190 0.216 2.290 2.074 -0.032 -0.006 fast_hv_lt
Path 2 can_top_level_inst/rst_sync_inst/rst:CLK can_top_level_inst/memory_registers_inst/soft_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q:ALn 0.190 0.216 2.290 2.074 -0.032 -0.006 fast_hv_lt
Path 3 can_top_level_inst/rst_sync_inst/rst:CLK can_top_level_inst/memory_registers_inst/control_registers_cs_reg:ALn 0.190 0.216 2.290 2.074 -0.032 -0.006 fast_hv_lt
Path 4 can_top_level_inst/rst_sync_inst/rst:CLK can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q:ALn 0.190 0.217 2.290 2.073 -0.032 -0.005 fast_hv_lt
Path 5 can_top_level_inst/rx_buffer_inst/rst_reg_inst/rx_shift_res_reg_inst/reg_q:CLK can_top_level_inst/rx_buffer_inst/commit_rx_frame:ALn 0.192 0.218 2.274 2.056 -0.032 -0.006 fast_hv_lt

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: can_top_level_inst/rst_sync_inst/rst:CLK
To: can_top_level_inst/memory_registers_inst/test_registers_cs_reg:ALn
data arrival time 2.290
data required time - 2.074
slack 0.216
Data arrival time calculation
SYS_CLK 0.000 0.000
clk_sys Clock source + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.795 0.795 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.262 1.057 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.087 1.144 1 r
I_1:A net clk_sys_ibuf_Z + 0.223 1.367 r
I_1:Y cell ADLIB:GB + 0.113 1.480 9 r
I_1/U0_RGB1_RGB0:A net I_1/U0_Y + 0.255 1.735 r
I_1/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.038 1.773 1943 f
can_top_level_inst/rst_sync_inst/rst:CLK net I_1/U0_RGB1_RGB0_rgb_net_1 + 0.327 2.100 r
can_top_level_inst/rst_sync_inst/rst:Q cell ADLIB:SLE + 0.078 2.178 10 r
can_top_level_inst/memory_registers_inst/test_registers_cs_reg:ALn net res_n_out_c + 0.112 2.290 r
data arrival time 2.290
Data required time calculation
SYS_CLK Clock Constraint 0.000 0.000
clk_sys Clock source + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.915 0.915 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.288 1.203 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.100 1.303 1 r
I_1:A net clk_sys_ibuf_Z + 0.244 1.547 r
I_1:Y cell ADLIB:GB + 0.124 1.671 9 r
I_1/U0_RGB1_RGB0:A net I_1/U0_Y + 0.282 1.953 r
I_1/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.043 1.996 1943 f
can_top_level_inst/memory_registers_inst/test_registers_cs_reg:CLK net I_1/U0_RGB1_RGB0_rgb_net_1 + 0.371 2.367 r
clock reconvergence pessimism + -0.261 2.106
can_top_level_inst/memory_registers_inst/test_registers_cs_reg:ALn Library removal time ADLIB:SLE + -0.032 2.074
data required time 2.074
Operating Conditions fast_hv_lt

SET External Removal

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Removal (ns) External Removal (ns) Operating Conditions
Path 1 res_n can_top_level_inst/rst_sync_inst/rst:ALn 1.987 1.987 -0.057 1.512 slow_lv_ht
Path 2 res_n can_top_level_inst/rst_sync_inst/rff:ALn 1.986 1.986 -0.057 1.512 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: res_n
To: can_top_level_inst/rst_sync_inst/rst:ALn
data arrival time 1.987
data required time - N/C
slack N/C
Data arrival time calculation
res_n 0.000 0.000 r
res_n_ibuf/U_IOPAD:PAD net res_n + 0.000 0.000 r
res_n_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.528 0.528 1 r
res_n_ibuf/U_IOIN:YIN net res_n_ibuf/YIN + 0.000 0.528 r
res_n_ibuf/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.302 0.830 2 r
can_top_level_inst/rst_sync_inst/rst:ALn net res_n_c + 1.157 1.987 r
data arrival time 1.987
Data required time calculation
SYS_CLK N/C N/C
clk_sys Clock source + 0.000 N/C r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 N/C r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.322 N/C 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.471 N/C r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.150 N/C 1 r
I_1:A net clk_sys_ibuf_Z + 0.383 N/C r
I_1:Y cell ADLIB:GB + 0.167 N/C 9 r
I_1/U0_RGB1_RGB0:A net I_1/U0_Y + 0.424 N/C r
I_1/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.059 N/C 1943 f
can_top_level_inst/rst_sync_inst/rst:CLK net I_1/U0_RGB1_RGB0_rgb_net_1 + 0.580 N/C r
can_top_level_inst/rst_sync_inst/rst:ALn Library removal time ADLIB:SLE + -0.057 N/C
Operating Conditions slow_lv_ht

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets