#Build: Synplify Pro (R) S-2021.09M, Build 223R, Feb 23 2022
#install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
#OS: Linux 
#Hostname: ondrej-Aspire-V3-771

# Mon Jul 18 09:34:51 2022

#Implementation: synthesis


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63079
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys HDL Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63079
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys VHDL Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 
@N: :  | stack limit increased to max 
@N: : ctu_can_fd_libero_top.vhd(90) | Top entity is set to ctu_can_fd_libero_top.
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst_ce.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_constants_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_frame_format.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_register_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_config_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/drv_stat_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/unary_ops_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/mux2.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_byte.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_preload.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sig_sync.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/access_signaler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/address_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_registers_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/cmn_reg_map_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/parity_calculator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_sync.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_types_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/id_transfer_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_destuffing.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_stuffing.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_traffic_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/crc_calc.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_crc.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_rules.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/operation_control.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/endian_swapper.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dlc_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/reintegration_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/retransmitt_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_shift_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_shift_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_core.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_err_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_edge_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trv_delay_meas.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_data_cache.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sample_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ssp_generator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_module.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/clk_gate.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_registers_reg_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/test_registers_reg_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/priority_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_filter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/range_filter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/frame_filters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_segment_meter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_generator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/segment_end_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/synchronisation_checker.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/prescaler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ctu_can_fd_libero_top.vhd'. 
VHDL syntax check successful!
@N:CD231 : std1164.vhd(889) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
@N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time.

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)


Process completed successfully.
# Mon Jul 18 09:34:52 2022

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63079
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Verilog Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/generic/acg5.v" (library work)
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v" (library work)
@W:CG100 : polarfire_syn_comps.v(21) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(61) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(88) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(118) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(168) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(213) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(232) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(281) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(335) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(657) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(761) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(795) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1059) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1369) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1396) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1441) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1474) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1492) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1518) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1559) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1581) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1599) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1616) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1635) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1652) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1681) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1712) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1802) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2026) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2187) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2203) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2219) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2235) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2267) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2648) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3661) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3732) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3861) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3879) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3896) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3911) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3926) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3953) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4065) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4096) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4142) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4252) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4436) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4477) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4503) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4520) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4597) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(5361) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6171) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6280) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6318) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6391) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(7280) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(8337) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(9296) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10032) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10747) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10781) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10817) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10864) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10898) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(11764) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12807) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12819) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12830) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12843) | User defined pragma syn_black_box detected

@N: :  | stack limit increased to max 
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB)


Process completed successfully.
# Mon Jul 18 09:34:52 2022

###########################################################]
###########################################################[
@N: :  | stack limit increased to max 
@N: : ctu_can_fd_libero_top.vhd(90) | Top entity is set to ctu_can_fd_libero_top.
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst_ce.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_constants_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_frame_format.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_register_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_config_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/drv_stat_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/unary_ops_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/mux2.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_byte.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_preload.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sig_sync.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/access_signaler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/address_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_registers_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/cmn_reg_map_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/parity_calculator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_sync.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_types_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/id_transfer_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_destuffing.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_stuffing.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_traffic_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/crc_calc.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_crc.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_rules.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/operation_control.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/endian_swapper.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dlc_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/reintegration_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/retransmitt_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_shift_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_shift_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_core.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_err_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_edge_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trv_delay_meas.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_data_cache.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sample_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ssp_generator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_module.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/clk_gate.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_registers_reg_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/test_registers_reg_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/priority_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_filter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/range_filter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/frame_filters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_segment_meter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_generator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/segment_end_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/synchronisation_checker.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/prescaler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ctu_can_fd_libero_top.vhd'. 
VHDL syntax check successful!
@N:CD231 : std1164.vhd(889) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
@N:CD630 : ctu_can_fd_libero_top.vhd(90) | Synthesizing ctu_can_fd_rtl.ctu_can_fd_libero_top.rtl.
@N:CD630 : can_top_level.vhd(103) | Synthesizing ctu_can_fd_rtl.can_top_level.rtl.
@N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time.
@N:CD630 : bus_sampling.vhd(97) | Synthesizing ctu_can_fd_rtl.bus_sampling.rtl.
@N:CD630 : sample_mux.vhd(93) | Synthesizing ctu_can_fd_rtl.sample_mux.rtl.
Post processing for ctu_can_fd_rtl.sample_mux.rtl
Running optimization stage 1 on sample_mux .......
Finished optimization stage 1 on sample_mux (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB)
@N:CD630 : bit_err_detector.vhd(95) | Synthesizing ctu_can_fd_rtl.bit_err_detector.rtl.
Post processing for ctu_can_fd_rtl.bit_err_detector.rtl
Running optimization stage 1 on bit_err_detector .......
Finished optimization stage 1 on bit_err_detector (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB)
@N:CD630 : tx_data_cache.vhd(94) | Synthesizing ctu_can_fd_rtl.tx_data_cache.rtl.
Post processing for ctu_can_fd_rtl.tx_data_cache.rtl
Running optimization stage 1 on tx_data_cache .......
Finished optimization stage 1 on tx_data_cache (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB)
@N:CD630 : ssp_generator.vhd(94) | Synthesizing ctu_can_fd_rtl.ssp_generator.rtl.
Post processing for ctu_can_fd_rtl.ssp_generator.rtl
Running optimization stage 1 on ssp_generator .......
Finished optimization stage 1 on ssp_generator (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : dff_arst.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst.rtl.
Post processing for ctu_can_fd_rtl.dff_arst.rtl
Running optimization stage 1 on dff_arst .......
Finished optimization stage 1 on dff_arst (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : rst_reg.vhd(82) | Synthesizing ctu_can_fd_rtl.rst_reg.rtl.
@N:CD630 : mux2.vhd(89) | Synthesizing ctu_can_fd_rtl.mux2.rtl.
Post processing for ctu_can_fd_rtl.mux2.rtl
Running optimization stage 1 on mux2 .......
Finished optimization stage 1 on mux2 (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
Post processing for ctu_can_fd_rtl.rst_reg.rtl
Running optimization stage 1 on rst_reg .......
Finished optimization stage 1 on rst_reg (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : data_edge_detector.vhd(109) | Synthesizing ctu_can_fd_rtl.data_edge_detector.rtl.
Post processing for ctu_can_fd_rtl.data_edge_detector.rtl
Running optimization stage 1 on data_edge_detector .......
Finished optimization stage 1 on data_edge_detector (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : trv_delay_meas.vhd(142) | Synthesizing ctu_can_fd_rtl.trv_delay_measurement.rtl.
Post processing for ctu_can_fd_rtl.trv_delay_measurement.rtl
Running optimization stage 1 on trv_delay_measurement .......
Finished optimization stage 1 on trv_delay_measurement (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : sig_sync.vhd(77) | Synthesizing ctu_can_fd_rtl.sig_sync.rtl.
Post processing for ctu_can_fd_rtl.sig_sync.rtl
Running optimization stage 1 on sig_sync .......
Finished optimization stage 1 on sig_sync (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
Post processing for ctu_can_fd_rtl.bus_sampling.rtl
Running optimization stage 1 on bus_sampling .......
Finished optimization stage 1 on bus_sampling (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : prescaler.vhd(100) | Synthesizing ctu_can_fd_rtl.prescaler.rtl.
@N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time.
@N:CD630 : trigger_generator.vhd(122) | Synthesizing ctu_can_fd_rtl.trigger_generator.rtl.
Post processing for ctu_can_fd_rtl.trigger_generator.rtl
Running optimization stage 1 on trigger_generator .......
Finished optimization stage 1 on trigger_generator (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : bit_time_fsm.vhd(95) | Synthesizing ctu_can_fd_rtl.bit_time_fsm.rtl.
@N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time.
Post processing for ctu_can_fd_rtl.bit_time_fsm.rtl
Running optimization stage 1 on bit_time_fsm .......
Finished optimization stage 1 on bit_time_fsm (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : segment_end_detector.vhd(96) | Synthesizing ctu_can_fd_rtl.segment_end_detector.rtl.
Post processing for ctu_can_fd_rtl.segment_end_detector.rtl
Running optimization stage 1 on segment_end_detector .......
Finished optimization stage 1 on segment_end_detector (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : bit_time_counters.vhd(98) | Synthesizing ctu_can_fd_rtl.bit_time_counters.rtl.
Post processing for ctu_can_fd_rtl.bit_time_counters.rtl
Running optimization stage 1 on bit_time_counters .......
Finished optimization stage 1 on bit_time_counters (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 150MB)
@N:CD630 : bit_segment_meter.vhd(196) | Synthesizing ctu_can_fd_rtl.bit_segment_meter.rtl.
Post processing for ctu_can_fd_rtl.bit_segment_meter.rtl
Running optimization stage 1 on bit_segment_meter .......
Finished optimization stage 1 on bit_segment_meter (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB)
@N:CD630 : synchronisation_checker.vhd(94) | Synthesizing ctu_can_fd_rtl.synchronisation_checker.rtl.
Post processing for ctu_can_fd_rtl.synchronisation_checker.rtl
Running optimization stage 1 on synchronisation_checker .......
Finished optimization stage 1 on synchronisation_checker (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB)
@N:CD630 : bit_time_cfg_capture.vhd(96) | Synthesizing ctu_can_fd_rtl.bit_time_cfg_capture.rtl.
Post processing for ctu_can_fd_rtl.bit_time_cfg_capture.rtl
Running optimization stage 1 on bit_time_cfg_capture .......
Finished optimization stage 1 on bit_time_cfg_capture (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB)
Post processing for ctu_can_fd_rtl.prescaler.rtl
Running optimization stage 1 on prescaler .......
Finished optimization stage 1 on prescaler (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB)
@N:CD630 : can_core.vhd(100) | Synthesizing ctu_can_fd_rtl.can_core.rtl.
@N:CD630 : trigger_mux.vhd(108) | Synthesizing ctu_can_fd_rtl.trigger_mux.rtl.
@N:CD630 : dff_arst_ce.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst_ce.rtl.
Post processing for ctu_can_fd_rtl.dff_arst_ce.rtl
Running optimization stage 1 on dff_arst_ce .......
Finished optimization stage 1 on dff_arst_ce (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
Post processing for ctu_can_fd_rtl.trigger_mux.rtl
Running optimization stage 1 on trigger_mux .......
Finished optimization stage 1 on trigger_mux (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
@N:CD630 : bus_traffic_counters.vhd(92) | Synthesizing ctu_can_fd_rtl.bus_traffic_counters.rtl.
Post processing for ctu_can_fd_rtl.bus_traffic_counters.rtl
Running optimization stage 1 on bus_traffic_counters .......
Finished optimization stage 1 on bus_traffic_counters (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
@N:CD630 : bit_destuffing.vhd(102) | Synthesizing ctu_can_fd_rtl.bit_destuffing.rtl.
@N:CD630 : dff_arst_ce.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst_ce.rtl.
Post processing for ctu_can_fd_rtl.dff_arst_ce.rtl
Running optimization stage 1 on dff_arst_ce .......
Finished optimization stage 1 on dff_arst_ce (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
@N:CD630 : dff_arst.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst.rtl.
Post processing for ctu_can_fd_rtl.dff_arst.rtl
Running optimization stage 1 on dff_arst .......
Finished optimization stage 1 on dff_arst (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
Post processing for ctu_can_fd_rtl.bit_destuffing.rtl
Running optimization stage 1 on bit_destuffing .......
Finished optimization stage 1 on bit_destuffing (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : bit_stuffing.vhd(100) | Synthesizing ctu_can_fd_rtl.bit_stuffing.rtl.
Post processing for ctu_can_fd_rtl.bit_stuffing.rtl
Running optimization stage 1 on bit_stuffing .......
Finished optimization stage 1 on bit_stuffing (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : can_crc.vhd(104) | Synthesizing ctu_can_fd_rtl.can_crc.rtl.
@N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl.
Post processing for ctu_can_fd_rtl.crc_calc.rtl
Running optimization stage 1 on crc_calc .......
Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl.
Post processing for ctu_can_fd_rtl.crc_calc.rtl
Running optimization stage 1 on crc_calc .......
Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl.
Post processing for ctu_can_fd_rtl.crc_calc.rtl
Running optimization stage 1 on crc_calc .......
Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
Post processing for ctu_can_fd_rtl.can_crc.rtl
Running optimization stage 1 on can_crc .......
Finished optimization stage 1 on can_crc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : fault_confinement.vhd(94) | Synthesizing ctu_can_fd_rtl.fault_confinement.rtl.
@N:CD630 : fault_confinement_rules.vhd(94) | Synthesizing ctu_can_fd_rtl.fault_confinement_rules.rtl.
Post processing for ctu_can_fd_rtl.fault_confinement_rules.rtl
Running optimization stage 1 on fault_confinement_rules .......
Finished optimization stage 1 on fault_confinement_rules (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : err_counters.vhd(100) | Synthesizing ctu_can_fd_rtl.err_counters.rtl.
Post processing for ctu_can_fd_rtl.err_counters.rtl
Running optimization stage 1 on err_counters .......
Finished optimization stage 1 on err_counters (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
@N:CD630 : fault_confinement_fsm.vhd(96) | Synthesizing ctu_can_fd_rtl.fault_confinement_fsm.rtl.
@N:CD233 : can_types_pkg.vhd(91) | Using sequential encoding for type t_fault_conf_state.
Post processing for ctu_can_fd_rtl.fault_confinement_fsm.rtl
Running optimization stage 1 on fault_confinement_fsm .......
Finished optimization stage 1 on fault_confinement_fsm (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
Post processing for ctu_can_fd_rtl.fault_confinement.rtl
Running optimization stage 1 on fault_confinement .......
Finished optimization stage 1 on fault_confinement (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
@N:CD630 : operation_control.vhd(93) | Synthesizing ctu_can_fd_rtl.operation_control.rtl.
@N:CD233 : can_types_pkg.vhd(98) | Using sequential encoding for type t_operation_control_state.
Post processing for ctu_can_fd_rtl.operation_control.rtl
Running optimization stage 1 on operation_control .......
Finished optimization stage 1 on operation_control (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
@N:CD630 : protocol_control.vhd(98) | Synthesizing ctu_can_fd_rtl.protocol_control.rtl.
@N:CD630 : rx_shift_reg.vhd(98) | Synthesizing ctu_can_fd_rtl.rx_shift_reg.rtl.
@N:CD630 : shift_reg_byte.vhd(85) | Synthesizing ctu_can_fd_rtl.shift_reg_byte.rtl.
Post processing for ctu_can_fd_rtl.shift_reg_byte.rtl
Running optimization stage 1 on shift_reg_byte .......
Finished optimization stage 1 on shift_reg_byte (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
Post processing for ctu_can_fd_rtl.rx_shift_reg.rtl
Running optimization stage 1 on rx_shift_reg .......
Finished optimization stage 1 on rx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
@N:CD630 : tx_shift_reg.vhd(95) | Synthesizing ctu_can_fd_rtl.tx_shift_reg.rtl.
@N:CD630 : shift_reg_preload.vhd(77) | Synthesizing ctu_can_fd_rtl.shift_reg_preload.rtl.
Post processing for ctu_can_fd_rtl.shift_reg_preload.rtl
Running optimization stage 1 on shift_reg_preload .......
Finished optimization stage 1 on shift_reg_preload (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
Post processing for ctu_can_fd_rtl.tx_shift_reg.rtl
Running optimization stage 1 on tx_shift_reg .......
Finished optimization stage 1 on tx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : err_detector.vhd(97) | Synthesizing ctu_can_fd_rtl.err_detector.rtl.
Post processing for ctu_can_fd_rtl.err_detector.rtl
Running optimization stage 1 on err_detector .......
Finished optimization stage 1 on err_detector (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : retransmitt_counter.vhd(95) | Synthesizing ctu_can_fd_rtl.retransmitt_counter.rtl.
Post processing for ctu_can_fd_rtl.retransmitt_counter.rtl
Running optimization stage 1 on retransmitt_counter .......
Finished optimization stage 1 on retransmitt_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : reintegration_counter.vhd(93) | Synthesizing ctu_can_fd_rtl.reintegration_counter.rtl.
Post processing for ctu_can_fd_rtl.reintegration_counter.rtl
Running optimization stage 1 on reintegration_counter .......
Finished optimization stage 1 on reintegration_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : control_counter.vhd(97) | Synthesizing ctu_can_fd_rtl.control_counter.rtl.
Post processing for ctu_can_fd_rtl.control_counter.rtl
Running optimization stage 1 on control_counter .......
Finished optimization stage 1 on control_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : protocol_control_fsm.vhd(110) | Synthesizing ctu_can_fd_rtl.protocol_control_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(106) | Using onehot encoding for type t_protocol_control_state. For example, enumeration s_pc_off is mapped to "10000000000000000000000000000000000000".
@N:CD630 : dlc_decoder.vhd(88) | Synthesizing ctu_can_fd_rtl.dlc_decoder.rtl.
Post processing for ctu_can_fd_rtl.dlc_decoder.rtl
Running optimization stage 1 on dlc_decoder .......
Finished optimization stage 1 on dlc_decoder (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 158MB)
Post processing for ctu_can_fd_rtl.protocol_control_fsm.rtl
Running optimization stage 1 on protocol_control_fsm .......
Finished optimization stage 1 on protocol_control_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : endian_swapper.vhd(95) | Synthesizing ctu_can_fd_rtl.endian_swapper.rtl.
Post processing for ctu_can_fd_rtl.endian_swapper.rtl
Running optimization stage 1 on endian_swapper .......
Finished optimization stage 1 on endian_swapper (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.protocol_control.rtl
Running optimization stage 1 on protocol_control .......
Finished optimization stage 1 on protocol_control (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.can_core.rtl
Running optimization stage 1 on can_core .......
Finished optimization stage 1 on can_core (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : int_manager.vhd(97) | Synthesizing ctu_can_fd_rtl.int_manager.rtl.
@N:CD630 : int_module.vhd(103) | Synthesizing ctu_can_fd_rtl.int_module.rtl.
Post processing for ctu_can_fd_rtl.int_module.rtl
Running optimization stage 1 on int_module .......
Finished optimization stage 1 on int_module (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.int_manager.rtl
Running optimization stage 1 on int_manager .......
Finished optimization stage 1 on int_manager (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : frame_filters.vhd(101) | Synthesizing ctu_can_fd_rtl.frame_filters.rtl.
@N:CD630 : range_filter.vhd(94) | Synthesizing ctu_can_fd_rtl.range_filter.rtl.
Post processing for ctu_can_fd_rtl.range_filter.rtl
Running optimization stage 1 on range_filter .......
Finished optimization stage 1 on range_filter (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : bit_filter.vhd(92) | Synthesizing ctu_can_fd_rtl.bit_filter.rtl.
Post processing for ctu_can_fd_rtl.bit_filter.rtl
Running optimization stage 1 on bit_filter .......
Finished optimization stage 1 on bit_filter (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.frame_filters.rtl
Running optimization stage 1 on frame_filters .......
Finished optimization stage 1 on frame_filters (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : tx_arbitrator.vhd(100) | Synthesizing ctu_can_fd_rtl.tx_arbitrator.rtl.
@N:CD630 : tx_arbitrator_fsm.vhd(98) | Synthesizing ctu_can_fd_rtl.tx_arbitrator_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(173) | Using onehot encoding for type t_tx_arb_state. For example, enumeration s_arb_idle is mapped to "10000000".
Post processing for ctu_can_fd_rtl.tx_arbitrator_fsm.rtl
Running optimization stage 1 on tx_arbitrator_fsm .......
Finished optimization stage 1 on tx_arbitrator_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : priority_decoder.vhd(96) | Synthesizing ctu_can_fd_rtl.priority_decoder.rtl.
@N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(278) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(278) | OTHERS clause is not synthesized.
Post processing for ctu_can_fd_rtl.priority_decoder.rtl
Running optimization stage 1 on priority_decoder .......
Finished optimization stage 1 on priority_decoder (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.tx_arbitrator.rtl
Running optimization stage 1 on tx_arbitrator .......
Finished optimization stage 1 on tx_arbitrator (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
@N:CD630 : parity_calculator.vhd(78) | Synthesizing ctu_can_fd_rtl.parity_calculator.rtl.
Post processing for ctu_can_fd_rtl.parity_calculator.rtl
Running optimization stage 1 on parity_calculator .......
Finished optimization stage 1 on parity_calculator (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : inf_ram_wrapper.vhd(85) | Synthesizing ctu_can_fd_rtl.inf_ram_wrapper.rtl.
Post processing for ctu_can_fd_rtl.inf_ram_wrapper.rtl
Running optimization stage 1 on inf_ram_wrapper .......
Finished optimization stage 1 on inf_ram_wrapper (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : clk_gate.vhd(83) | Synthesizing ctu_can_fd_rtl.clk_gate.rtl.
Post processing for ctu_can_fd_rtl.clk_gate.rtl
Running optimization stage 1 on clk_gate .......
Finished optimization stage 1 on clk_gate (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 185MB)
@N:CD630 : rx_buffer.vhd(99) | Synthesizing ctu_can_fd_rtl.rx_buffer.rtl.
@N:CD364 : rx_buffer.vhd(793) | Removing redundant assignment.
@N:CD364 : rx_buffer.vhd(824) | Removing redundant assignment.
@N:CD630 : rx_buffer_ram.vhd(105) | Synthesizing ctu_can_fd_rtl.rx_buffer_ram.rtl.
@N:CD630 : inf_ram_wrapper.vhd(85) | Synthesizing ctu_can_fd_rtl.inf_ram_wrapper.rtl.
Post processing for ctu_can_fd_rtl.inf_ram_wrapper.rtl
Running optimization stage 1 on inf_ram_wrapper .......
Finished optimization stage 1 on inf_ram_wrapper (CPU Time 0h:00m:00s, Memory Used current: 182MB peak: 185MB)
Post processing for ctu_can_fd_rtl.rx_buffer_ram.rtl
Running optimization stage 1 on rx_buffer_ram .......
Finished optimization stage 1 on rx_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 186MB)
@N:CD630 : rx_buffer_pointers.vhd(101) | Synthesizing ctu_can_fd_rtl.rx_buffer_pointers.rtl.
Post processing for ctu_can_fd_rtl.rx_buffer_pointers.rtl
Running optimization stage 1 on rx_buffer_pointers .......
Finished optimization stage 1 on rx_buffer_pointers (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 186MB)
@N:CD630 : rx_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.rx_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(161) | Using onehot encoding for type t_rx_buf_state. For example, enumeration s_rxb_idle is mapped to "10000000".
Post processing for ctu_can_fd_rtl.rx_buffer_fsm.rtl
Running optimization stage 1 on rx_buffer_fsm .......
Finished optimization stage 1 on rx_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 186MB)
Post processing for ctu_can_fd_rtl.rx_buffer.rtl
Running optimization stage 1 on rx_buffer .......
Finished optimization stage 1 on rx_buffer (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 186MB)
@N:CD630 : memory_registers.vhd(97) | Synthesizing ctu_can_fd_rtl.memory_registers.rtl.
@N:CD630 : test_registers_reg_map.vhd(81) | Synthesizing ctu_can_fd_rtl.test_registers_reg_map.rtl.
@N:CD630 : data_mux.vhd(74) | Synthesizing ctu_can_fd_rtl.data_mux.rtl.
Post processing for ctu_can_fd_rtl.data_mux.rtl
Running optimization stage 1 on data_mux .......
Finished optimization stage 1 on data_mux (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 193MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 193MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 194MB peak: 194MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 194MB peak: 194MB)
@N:CD630 : address_decoder.vhd(41) | Synthesizing ctu_can_fd_rtl.address_decoder.rtl.
Post processing for ctu_can_fd_rtl.address_decoder.rtl
Running optimization stage 1 on address_decoder .......
Finished optimization stage 1 on address_decoder (CPU Time 0h:00m:00s, Memory Used current: 194MB peak: 194MB)
Post processing for ctu_can_fd_rtl.test_registers_reg_map.rtl
Running optimization stage 1 on test_registers_reg_map .......
Finished optimization stage 1 on test_registers_reg_map (CPU Time 0h:00m:00s, Memory Used current: 194MB peak: 194MB)
@N:CD630 : control_registers_reg_map.vhd(81) | Synthesizing ctu_can_fd_rtl.control_registers_reg_map.rtl.
@N:CD630 : data_mux.vhd(74) | Synthesizing ctu_can_fd_rtl.data_mux.rtl.
Post processing for ctu_can_fd_rtl.data_mux.rtl
Running optimization stage 1 on data_mux .......
Finished optimization stage 1 on data_mux (CPU Time 0h:00m:03s, Memory Used current: 373MB peak: 373MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB)

Only the first 100 messages of id 'CD630' are reported. To see all messages use 'report_messages -log /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/synlog/ctu_can_fd_libero_top_compiler.srr -id CD630' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CD630} -count unlimited' in the Tcl shell.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB)
Post processing for ctu_can_fd_rtl.access_signaller.rtl
Running optimization stage 1 on access_signaller .......
Finished optimization stage 1 on access_signaller (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 373MB peak: 373MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 374MB peak: 374MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 374MB peak: 374MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 374MB peak: 374MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 374MB peak: 374MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 375MB peak: 375MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 375MB peak: 375MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 375MB peak: 375MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 375MB peak: 375MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Post processing for ctu_can_fd_rtl.address_decoder.rtl
Running optimization stage 1 on address_decoder .......
Finished optimization stage 1 on address_decoder (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Post processing for ctu_can_fd_rtl.control_registers_reg_map.rtl
Running optimization stage 1 on control_registers_reg_map .......
Finished optimization stage 1 on control_registers_reg_map (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Post processing for ctu_can_fd_rtl.memory_registers.rtl
Running optimization stage 1 on memory_registers .......
Finished optimization stage 1 on memory_registers (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Post processing for ctu_can_fd_rtl.rst_sync.rtl
Running optimization stage 1 on rst_sync .......
Finished optimization stage 1 on rst_sync (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Post processing for ctu_can_fd_rtl.can_top_level.rtl
Running optimization stage 1 on can_top_level .......
Finished optimization stage 1 on can_top_level (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Post processing for ctu_can_fd_rtl.ctu_can_fd_libero_top.rtl
Running optimization stage 1 on ctu_can_fd_libero_top .......
Finished optimization stage 1 on ctu_can_fd_libero_top (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on rst_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on rst_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 .......
@N:CL159 : address_decoder.vhd(64) | Input clk_sys is unused.
@N:CL159 : address_decoder.vhd(65) | Input res_n is unused.
Finished optimization stage 2 on address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_3layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_4layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_5layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 11 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : memory_reg.vhd(76) | Input port bit 0 of data_in(31 downto 0) is unused 
@W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 2 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(70) | Input clk_sys is unused.
@N:CL159 : memory_reg.vhd(71) | Input res_n is unused.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_5layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(70) | Input clk_sys is unused.
@N:CL159 : memory_reg.vhd(71) | Input res_n is unused.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_6layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0 .......
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_7layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0 .......
@W:CL247 : memory_reg.vhd(76) | Input port bit 18 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 12 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 6 of data_in(31 downto 0) is unused 
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_8layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0 .......
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_9layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0 .......
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_10layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 13 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 2 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_11layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 29 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_12layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0 .......
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_13layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 7 to 1 of data_in(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_14layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on access_signaller_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@N:CL159 : access_signaler.vhd(65) | Input clk_sys is unused.
@N:CL159 : access_signaler.vhd(66) | Input res_n is unused.
@N:CL159 : access_signaler.vhd(77) | Input write is unused.
Finished optimization stage 2 on access_signaller_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 7 to 3 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_15layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0 .......
@W:CL247 : memory_reg.vhd(76) | Input port bit 31 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 27 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 23 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 19 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 15 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 11 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 7 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 3 of data_in(31 downto 0) is unused 
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_16layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 10 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_17layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 .......
Finished optimization stage 2 on data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@W:CL246 : control_registers_reg_map.vhd(97) | Input port bits 15 to 8 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : control_registers_reg_map.vhd(97) | Input port bits 1 to 0 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on control_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@N:CL159 : address_decoder.vhd(64) | Input clk_sys is unused.
@N:CL159 : address_decoder.vhd(65) | Input res_n is unused.
Finished optimization stage 2 on address_decoder_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 2 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 1 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 20 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : memory_reg.vhd(79) | Input port bit 3 of w_be(3 downto 0) is unused 
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 .......
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on data_mux_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@W:CL246 : test_registers_reg_map.vhd(92) | Input port bits 15 to 8 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : test_registers_reg_map.vhd(92) | Input port bits 1 to 0 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : test_registers_reg_map.vhd(100) | Input lock_2 is unused.
Finished optimization stage 2 on test_registers_reg_map_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 376MB)
Running optimization stage 2 on memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@W:CL246 : memory_registers.vhd(196) | Input port bits 511 to 386 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : memory_registers.vhd(196) | Input port bit 383 of stat_bus(511 downto 0) is unused 
@W:CL246 : memory_registers.vhd(196) | Input port bits 369 to 306 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 299 to 297 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 256 to 252 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 187 to 110 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 98 to 90 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : memory_registers.vhd(196) | Input port bit 80 of stat_bus(511 downto 0) is unused 
@W:CL246 : memory_registers.vhd(196) | Input port bits 70 to 10 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 8 to 6 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on rx_buffer_fsm .......
@N:CL201 : rx_buffer_fsm.vhd(311) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on rx_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on rx_buffer_pointers_128 .......
Finished optimization stage 2 on rx_buffer_pointers_128 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on inf_ram_wrapper_32_128_12_true_true .......
@W:CL246 : inf_ram_wrapper.vhd(114) | Input port bits 11 to 7 of addr_a(11 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : inf_ram_wrapper.vhd(129) | Input port bits 11 to 7 of addr_b(11 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on inf_ram_wrapper_32_128_12_true_true (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on rx_buffer_ram_128_true_true .......
@N:CL134 : rx_buffer_ram.vhd(237) | Found RAM parity, depth=128, width=1
@W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 47 to 44 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on rx_buffer_ram_128_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on rx_buffer_128_true_true_1 .......
@W:CL246 : rx_buffer.vhd(224) | Input port bits 1023 to 477 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : rx_buffer.vhd(224) | Input port bits 475 to 355 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : rx_buffer.vhd(224) | Input port bits 349 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on rx_buffer_128_true_true_1 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_ram_0_true_true .......
@N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_0_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_fsm_0 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_8_0_1_true_true .......
@W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 1 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : txt_buffer.vhd(165) | Input drv_txbbm_ena is unused.
Finished optimization stage 2 on txt_buffer_8_0_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_ram_1_true_true .......
@N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_fsm_1 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_1 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_8_1_1_true_true .......
@W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 2 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : txt_buffer.vhd(150) | Input port bit 0 of txtb_sw_cmd_index(7 downto 0) is unused 
Finished optimization stage 2 on txt_buffer_8_1_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_ram_2_true_true .......
@N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_2_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_fsm_2 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_2 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_8_2_1_true_true .......
@W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 3 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer.vhd(150) | Input port bits 1 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : txt_buffer.vhd(165) | Input drv_txbbm_ena is unused.
Finished optimization stage 2 on txt_buffer_8_2_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_ram_3_true_true .......
@N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_3_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_fsm_3 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_3 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_8_3_1_true_true .......
@W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 4 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer.vhd(150) | Input port bits 2 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_8_3_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_ram_4_true_true .......
@N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_4_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_fsm_4 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_4 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_8_4_1_true_true .......
@W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 5 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer.vhd(150) | Input port bits 3 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : txt_buffer.vhd(165) | Input drv_txbbm_ena is unused.
Finished optimization stage 2 on txt_buffer_8_4_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_ram_5_true_true .......
@N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_5_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_fsm_5 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_5 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_8_5_1_true_true .......
@W:CL246 : txt_buffer.vhd(150) | Input port bits 7 to 6 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer.vhd(150) | Input port bits 4 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_8_5_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_ram_6_true_true .......
@N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_6_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_fsm_6 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_6 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on txt_buffer_8_6_1_true_true .......
@W:CL247 : txt_buffer.vhd(150) | Input port bit 7 of txtb_sw_cmd_index(7 downto 0) is unused 
@W:CL246 : txt_buffer.vhd(150) | Input port bits 5 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : txt_buffer.vhd(165) | Input drv_txbbm_ena is unused.
Finished optimization stage 2 on txt_buffer_8_6_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on clk_gate_1 .......
@N:CL159 : clk_gate.vhd(92) | Input clk_en is unused.
@N:CL159 : clk_gate.vhd(95) | Input scan_enable is unused.
Finished optimization stage 2 on clk_gate_1 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 377MB)
Running optimization stage 2 on inf_ram_wrapper_32_21_5_true_true .......
Finished optimization stage 2 on inf_ram_wrapper_32_21_5_true_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on parity_calculator_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on txt_buffer_ram_7_true_true .......
@N:CL134 : txt_buffer_ram.vhd(235) | Found RAM parity, depth=21, width=1
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_7_true_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on txt_buffer_fsm_7 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_7 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on txt_buffer_8_7_1_true_true .......
@W:CL246 : txt_buffer.vhd(150) | Input port bits 6 to 0 of txtb_sw_cmd_index(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_8_7_1_true_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on priority_decoder_8 .......
Finished optimization stage 2 on priority_decoder_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on tx_arbitrator_fsm .......
@N:CL201 : tx_arbitrator_fsm.vhd(524) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@W:CL246 : tx_arbitrator_fsm.vhd(128) | Input port bits 5 to 2 of txtb_hw_cmd(5 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on tx_arbitrator_fsm (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on tx_arbitrator_8 .......
@W:CL247 : tx_arbitrator.vhd(125) | Input port bit 7 of txtb_allow_bb(7 downto 0) is unused 
@W:CL247 : tx_arbitrator.vhd(125) | Input port bit 5 of txtb_allow_bb(7 downto 0) is unused 
@W:CL247 : tx_arbitrator.vhd(125) | Input port bit 3 of txtb_allow_bb(7 downto 0) is unused 
@W:CL247 : tx_arbitrator.vhd(125) | Input port bit 1 of txtb_allow_bb(7 downto 0) is unused 
@W:CL246 : tx_arbitrator.vhd(200) | Input port bits 1023 to 477 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : tx_arbitrator.vhd(200) | Input port bits 474 to 473 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : tx_arbitrator.vhd(200) | Input port bits 471 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on tx_arbitrator_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bit_filter_29_true .......
Finished optimization stage 2 on bit_filter_29_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on range_filter_29_true .......
Finished optimization stage 2 on range_filter_29_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on frame_filters_true_true_true_true .......
@W:CL246 : frame_filters.vhd(129) | Input port bits 1023 to 331 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : frame_filters.vhd(129) | Input port bits 80 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on frame_filters_true_true_true_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on int_module .......
Finished optimization stage 2 on int_module (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on int_manager_12_8 .......
@W:CL246 : int_manager.vhd(157) | Input port bits 1023 to 876 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 863 to 844 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 831 to 812 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 799 to 780 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 767 to 748 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 735 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on int_manager_12_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on endian_swapper_true_4_8 .......
Finished optimization stage 2 on endian_swapper_true_4_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on dlc_decoder .......
Finished optimization stage 2 on dlc_decoder (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on protocol_control_fsm .......
@N:CL201 : protocol_control_fsm.vhd(2988) | Trying to extract state machine for register sp_control_q_i.
Extracted state machine for register sp_control_q_i
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : protocol_control_fsm.vhd(2840) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 38 reachable states with original encodings of:
   00000000000000000000000000000000000001
   00000000000000000000000000000000000010
   00000000000000000000000000000000000100
   00000000000000000000000000000000001000
   00000000000000000000000000000000010000
   00000000000000000000000000000000100000
   00000000000000000000000000000001000000
   00000000000000000000000000000010000000
   00000000000000000000000000000100000000
   00000000000000000000000000001000000000
   00000000000000000000000000010000000000
   00000000000000000000000000100000000000
   00000000000000000000000001000000000000
   00000000000000000000000010000000000000
   00000000000000000000000100000000000000
   00000000000000000000001000000000000000
   00000000000000000000010000000000000000
   00000000000000000000100000000000000000
   00000000000000000001000000000000000000
   00000000000000000010000000000000000000
   00000000000000000100000000000000000000
   00000000000000001000000000000000000000
   00000000000000010000000000000000000000
   00000000000000100000000000000000000000
   00000000000001000000000000000000000000
   00000000000010000000000000000000000000
   00000000000100000000000000000000000000
   00000000001000000000000000000000000000
   00000000010000000000000000000000000000
   00000000100000000000000000000000000000
   00000001000000000000000000000000000000
   00000010000000000000000000000000000000
   00000100000000000000000000000000000000
   00001000000000000000000000000000000000
   00010000000000000000000000000000000000
   00100000000000000000000000000000000000
   01000000000000000000000000000000000000
   10000000000000000000000000000000000000
Finished optimization stage 2 on protocol_control_fsm (CPU Time 0h:00m:02s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on control_counter_9 .......
Finished optimization stage 2 on control_counter_9 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on reintegration_counter .......
Finished optimization stage 2 on reintegration_counter (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on retransmitt_counter_4 .......
Finished optimization stage 2 on retransmitt_counter_4 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on err_detector_true .......
Finished optimization stage 2 on err_detector_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on shift_reg_preload_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on tx_shift_reg .......
Finished optimization stage 2 on tx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@W:CL247 : shift_reg_byte.vhd(117) | Input port bit 0 of byte_input_sel(3 downto 0) is unused 
Finished optimization stage 2 on shift_reg_byte_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on rx_shift_reg .......
Finished optimization stage 2 on rx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on protocol_control_9_4_true .......
@W:CL246 : protocol_control.vhd(128) | Input port bits 1023 to 514 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 506 to 478 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 476 to 472 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 464 to 461 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 459 to 430 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 428 to 375 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 372 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on protocol_control_9_4_true (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on operation_control .......
@N:CL201 : operation_control.vhd(227) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on operation_control (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on fault_confinement_fsm .......
@N:CL201 : fault_confinement_fsm.vhd(274) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Finished optimization stage 2 on fault_confinement_fsm (CPU Time 0h:00m:01s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on err_counters .......
Finished optimization stage 2 on err_counters (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on fault_confinement_rules .......
@N:CL159 : fault_confinement_rules.vhd(100) | Input clk_sys is unused.
Finished optimization stage 2 on fault_confinement_rules (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on fault_confinement .......
@W:CL246 : fault_confinement.vhd(114) | Input port bits 1023 to 514 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : fault_confinement.vhd(114) | Input port bits 512 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : fault_confinement.vhd(114) | Input port bits 508 to 427 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : fault_confinement.vhd(114) | Input port bits 399 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : fault_confinement.vhd(163) | Input rec_valid is unused.
Finished optimization stage 2 on fault_confinement (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 .......
Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 .......
Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_2layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@W:CL246 : can_crc.vhd(129) | Input port bits 1023 to 511 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : can_crc.vhd(129) | Input port bits 509 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on can_crc_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bit_stuffing .......
Finished optimization stage 2 on bit_stuffing (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 .......
Finished optimization stage 2 on dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 .......
Finished optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bit_destuffing .......
Finished optimization stage 2 on bit_destuffing (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bus_traffic_counters .......
Finished optimization stage 2 on bus_traffic_counters (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on trigger_mux_2 .......
Finished optimization stage 2 on trigger_mux_2 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bit_time_cfg_capture_8_8_8_5_8_8_8_5 .......
@W:CL246 : bit_time_cfg_capture.vhd(136) | Input port bits 1023 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : bit_time_cfg_capture.vhd(136) | Input port bits 508 to 61 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on bit_time_cfg_capture_8_8_8_5_8_8_8_5 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on synchronisation_checker .......
Finished optimization stage 2 on synchronisation_checker (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bit_segment_meter_5_8_8_9 .......
Finished optimization stage 2 on bit_segment_meter_5_8_8_9 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bit_time_counters_9_8 .......
Finished optimization stage 2 on bit_time_counters_9_8 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on segment_end_detector .......
Finished optimization stage 2 on segment_end_detector (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bit_time_fsm .......
@N:CL201 : bit_time_fsm.vhd(208) | Trying to extract state machine for register current_state.
Extracted state machine for register current_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Finished optimization stage 2 on bit_time_fsm (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on trigger_generator_2 .......
Finished optimization stage 2 on trigger_generator_2 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on prescaler_8_8_8_5_8_8_8_5_2 .......
Finished optimization stage 2 on prescaler_8_8_8_5_8_8_8_5_2 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on sig_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on sig_sync_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on trv_delay_measurement_7_8_true_255 .......
Finished optimization stage 2 on trv_delay_measurement_7_8_true_255 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on data_edge_detector .......
Finished optimization stage 2 on data_edge_detector (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on mux2 .......
Finished optimization stage 2 on mux2 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
Finished optimization stage 2 on dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on ssp_generator_15 .......
Finished optimization stage 2 on ssp_generator_15 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 .......
@N:CL134 : tx_data_cache.vhd(189) | Found RAM tx_cache, depth=8, width=1
Finished optimization stage 2 on tx_data_cache_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bit_err_detector .......
Finished optimization stage 2 on bit_err_detector (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on sample_mux .......
Finished optimization stage 2 on sample_mux (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on bus_sampling_255_8_7_8_true_15 .......
@W:CL246 : bus_sampling.vhd(145) | Input port bits 1023 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : bus_sampling.vhd(145) | Input port bits 508 to 383 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : bus_sampling.vhd(145) | Input port bits 372 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on bus_sampling_255_8_7_8_true_15 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 .......
Finished optimization stage 2 on can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)
Running optimization stage 2 on ctu_can_fd_libero_top .......
Finished optimization stage 2 on ctu_can_fd_libero_top (CPU Time 0h:00m:00s, Memory Used current: 382MB peak: 382MB)

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_vhdl Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 382MB peak: 382MB)


Process completed successfully.
# Mon Jul 18 09:35:08 2022

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63079
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Jul 18 09:35:08 2022

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  ctu_can_fd_libero_top_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 43MB peak: 43MB)

Process took 0h:00m:16s realtime, 0h:00m:15s cputime

Process completed successfully.
# Mon Jul 18 09:35:08 2022

###########################################################]


###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63079
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 164MB peak: 164MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Jul 18 09:35:11 2022

###########################################################]


Premap Report



# Mon Jul 18 09:35:11 2022


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63079
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Generic Technology Pre-mapping, Version map202109act, Build 055R, Built Feb 23 2022 09:46:51, @4155246


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 222MB peak: 222MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 241MB peak: 241MB)

Reading constraint file: /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/designer/ctu_can_fd_libero_top/synthesis.fdc
Reading constraint file: /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/constraint/ctu_can_fd_top.fdc
Linked File:  ctu_can_fd_libero_top_scck.rpt
See clock summary report "/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/ctu_can_fd_libero_top_scck.rpt"
@N:MF472 :  | Synthesis running in Automatic Compile Point mode 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 270MB peak: 270MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 270MB peak: 270MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 274MB peak: 274MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 277MB peak: 277MB)


Starting HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 332MB peak: 332MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 332MB peak: 332MB)


Start optimization across hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 332MB peak: 332MB)

NConnInternalConnection caching in on
@N:BN115 : txt_buffer.vhd(348) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_8_0_1_true_true(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(348) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_8_1_1_true_true(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(348) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_8_2_1_true_true(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(348) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_8_3_1_true_true(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(348) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_8_4_1_true_true(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(348) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_8_5_1_true_true(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(348) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_8_6_1_true_true(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(348) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_8_7_1_true_true(rtl)) because it does not drive other instances.
@W:BN132 : tx_arbitrator.vhd(761) | Removing sequential instance can_top_level_inst.tx_arbitrator_inst.txtb_pointer_meta_q[4] because it is equivalent to instance can_top_level_inst.tx_arbitrator_inst.txtb_pointer_meta_q[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_8(rtl)) because it does not drive other instances.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_7(rtl)) because it does not drive other instances.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_4(rtl)) because it does not drive other instances.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_3(rtl)) because it does not drive other instances.
@N:BN115 : protocol_control.vhd(689) | Removing instance endian_swapper_tx_inst (in view: ctu_can_fd_rtl.protocol_control_9_4_true(rtl)) because it does not drive other instances.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_5(rtl)) because it does not drive other instances.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_6(rtl)) because it does not drive other instances.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_2(rtl)) because it does not drive other instances.
@N:BN115 : rx_buffer.vhd(841) | Removing instance clk_gate_rx_buffer_ram_comp (in view: ctu_can_fd_rtl.rx_buffer_128_true_true_1(rtl)) because it does not drive other instances.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1(rtl)) because it does not drive other instances.
@N:BN115 : rst_reg.vhd(133) | Removing instance mux2_res_tst_inst (in view: ctu_can_fd_rtl.rst_reg_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_0(rtl)) because it does not drive other instances.
@N:BN115 : memory_registers.vhd(505) | Removing instance clk_gate_control_regs_comp (in view: ctu_can_fd_rtl.memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl)) because it does not drive other instances.
@N:BN115 : memory_registers.vhd(517) | Removing instance clk_gate_test_regs_comp (in view: ctu_can_fd_rtl.memory_registers_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl)) because it does not drive other instances.

Finished optimization across hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 332MB peak: 332MB)

@N:FP130 :  | Promoting Net clk_sys on CLKINT  I_1  
@N:FP130 :  | Promoting Net can_top_level_inst.memory_registers_inst.global_rst_rst_reg_inst.rx_shift_res_reg_inst.reg_q_arst on CLKINT  I_2  
@N:FX1184 :  | Applying syn_allowed_resources blockrams=952 on top level netlist ctu_can_fd_libero_top  

Finished netlist restructuring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 340MB peak: 340MB)



Clock Summary
******************

          Start       Requested     Requested     Clock        Clock                Clock
Level     Clock       Frequency     Period        Type         Group                Load 
-----------------------------------------------------------------------------------------
0 -       SYS_CLK     100.0 MHz     10.000        declared     default_clkgroup     11242
=========================================================================================



Clock Load Summary
***********************

            Clock     Source            Clock Pin                                                                Non-clock Pin     Non-clock Pin
Clock       Load      Pin               Seq Example                                                              Seq Example       Comb Example 
------------------------------------------------------------------------------------------------------------------------------------------------
SYS_CLK     11242     clk_sys(port)     can_top_level_inst.bus_sampling_inst.sample_mux_inst.prev_sample_q.C     -                 I_1.A(CLKINT)
================================================================================================================================================

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/ctu_can_fd_libero_top.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 340MB peak: 340MB)

Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.rx_buffer_fsm(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_5(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_7(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_3(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_1(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_4(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_0(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_6(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_2(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.tx_arbitrator_fsm(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine sp_control_q_i[0:2] (in view: ctu_can_fd_rtl.protocol_control_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine curr_state[0:37] (in view: ctu_can_fd_rtl.protocol_control_fsm(rtl))
original code -> new code
   00000000000000000000000000000000000001 -> 00000000000000000000000000000000000001
   00000000000000000000000000000000000010 -> 00000000000000000000000000000000000010
   00000000000000000000000000000000000100 -> 00000000000000000000000000000000000100
   00000000000000000000000000000000001000 -> 00000000000000000000000000000000001000
   00000000000000000000000000000000010000 -> 00000000000000000000000000000000010000
   00000000000000000000000000000000100000 -> 00000000000000000000000000000000100000
   00000000000000000000000000000001000000 -> 00000000000000000000000000000001000000
   00000000000000000000000000000010000000 -> 00000000000000000000000000000010000000
   00000000000000000000000000000100000000 -> 00000000000000000000000000000100000000
   00000000000000000000000000001000000000 -> 00000000000000000000000000001000000000
   00000000000000000000000000010000000000 -> 00000000000000000000000000010000000000
   00000000000000000000000000100000000000 -> 00000000000000000000000000100000000000
   00000000000000000000000001000000000000 -> 00000000000000000000000001000000000000
   00000000000000000000000010000000000000 -> 00000000000000000000000010000000000000
   00000000000000000000000100000000000000 -> 00000000000000000000000100000000000000
   00000000000000000000001000000000000000 -> 00000000000000000000001000000000000000
   00000000000000000000010000000000000000 -> 00000000000000000000010000000000000000
   00000000000000000000100000000000000000 -> 00000000000000000000100000000000000000
   00000000000000000001000000000000000000 -> 00000000000000000001000000000000000000
   00000000000000000010000000000000000000 -> 00000000000000000010000000000000000000
   00000000000000000100000000000000000000 -> 00000000000000000100000000000000000000
   00000000000000001000000000000000000000 -> 00000000000000001000000000000000000000
   00000000000000010000000000000000000000 -> 00000000000000010000000000000000000000
   00000000000000100000000000000000000000 -> 00000000000000100000000000000000000000
   00000000000001000000000000000000000000 -> 00000000000001000000000000000000000000
   00000000000010000000000000000000000000 -> 00000000000010000000000000000000000000
   00000000000100000000000000000000000000 -> 00000000000100000000000000000000000000
   00000000001000000000000000000000000000 -> 00000000001000000000000000000000000000
   00000000010000000000000000000000000000 -> 00000000010000000000000000000000000000
   00000000100000000000000000000000000000 -> 00000000100000000000000000000000000000
   00000001000000000000000000000000000000 -> 00000001000000000000000000000000000000
   00000010000000000000000000000000000000 -> 00000010000000000000000000000000000000
   00000100000000000000000000000000000000 -> 00000100000000000000000000000000000000
   00001000000000000000000000000000000000 -> 00001000000000000000000000000000000000
   00010000000000000000000000000000000000 -> 00010000000000000000000000000000000000
   00100000000000000000000000000000000000 -> 00100000000000000000000000000000000000
   01000000000000000000000000000000000000 -> 01000000000000000000000000000000000000
   10000000000000000000000000000000000000 -> 10000000000000000000000000000000000000
Encoding state machine curr_state[0:3] (in view: ctu_can_fd_rtl.operation_control(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : operation_control.vhd(227) | There are no possible illegal states for state machine curr_state[0:3] (in view: ctu_can_fd_rtl.operation_control(rtl)); safe FSM implementation is not required.
Encoding state machine curr_state[0:2] (in view: ctu_can_fd_rtl.fault_confinement_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine current_state[0:2] (in view: ctu_can_fd_rtl.bit_time_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 358MB peak: 358MB)


Finished constraint checker (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 366MB peak: 366MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 366MB peak: 366MB)

Process took 0h:00m:12s realtime, 0h:00m:11s cputime
# Mon Jul 18 09:35:24 2022

###########################################################]


Map & Optimize Report



# Mon Jul 18 09:35:25 2022


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63079
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Generic Technology Mapper, Version map202109act, Build 055R, Built Feb 23 2022 09:46:51, @4155246


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 222MB peak: 222MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 233MB peak: 233MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 233MB peak: 233MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 233MB peak: 233MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 233MB peak: 233MB)


@N:MF104 : inf_ram_wrapper.vhd(85) | Found compile point of type hard on View view:ctu_can_fd_rtl.inf_ram_wrapper_32_128_12_true_true(rtl) 
@N:MF104 : can_core.vhd(100) | Found compile point of type hard on View view:ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl) 
@N:MF104 : can_top_level.vhd(103) | Found compile point of type hard on View view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) 

Synthesis running in Multiprocessing mode
Maximum number of parallel jobs set to 4
Multiprocessing started at : Mon Jul 18 09:35:25 2022
@W:BN114 :  | Removing instance CP_fanout_cell_ctu_can_fd_libero_top_rtl_inst (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_acp(rtl)) because it does not drive other instances. 
Mapping can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 as a separate process
@N:MF107 : inf_ram_wrapper.vhd(85) | Old database up-to-date, remapping Compile point view:ctu_can_fd_rtl.inf_ram_wrapper_32_128_12_true_true(rtl) unnecessary 
@N:MF107 : can_core.vhd(100) | Old database up-to-date, remapping Compile point view:ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl) unnecessary 
@N:MF107 : ctu_can_fd_libero_top.vhd(90) | Old database up-to-date, remapping Compile point view:ctu_can_fd_rtl.ctu_can_fd_libero_top(rtl) unnecessary 
MCP Status: 1 jobs running

@N:MF106 : can_top_level.vhd(103) | Mapping Compile point view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) because 
		 RTL and/or Constraints changed.


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 312MB peak: 312MB)


Available hyper_sources - for debug and ip models
	None Found


#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####
@W:FA239 : rx_buffer.vhd(628) | ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W:FA239 : rx_buffer.vhd(628) | ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N:MO106 : rx_buffer.vhd(628) | Found ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 16 words by 5 bits.

Finished RTL optimizations (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 327MB peak: 327MB)

@N:MF135 : txt_buffer_ram.vhd(235) | RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N:MF135 : txt_buffer_ram.vhd(235) | RAM txt_buf_comp_gen\.6\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N:MF135 : txt_buffer_ram.vhd(235) | RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N:MF135 : txt_buffer_ram.vhd(235) | RAM txt_buf_comp_gen\.4\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N:MF135 : txt_buffer_ram.vhd(235) | RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N:MF135 : txt_buffer_ram.vhd(235) | RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N:MF135 : txt_buffer_ram.vhd(235) | RAM txt_buf_comp_gen\.7\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N:MF135 : txt_buffer_ram.vhd(235) | RAM txt_buf_comp_gen\.5\.txt_buffer_inst.txt_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 32 words by 1 bits.
@N:MF135 : rx_buffer_ram.vhd(237) | RAM rx_buffer_inst.rx_buffer_ram_inst.parity (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) is 128 words by 1 bits.
@N:MO231 : rx_buffer_pointers.vhd(285) | Found counter in view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) instance rx_buffer_inst.rx_buffer_pointers_inst.write_pointer_raw_i[6:0] 
@N:MO231 : rx_buffer_pointers.vhd(308) | Found counter in view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) instance rx_buffer_inst.rx_buffer_pointers_inst.write_pointer_ts_i[6:0] 
@N:MO231 : rx_buffer.vhd(699) | Found counter in view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) instance rx_buffer_inst.read_counter_q[4:0] 
@N:MF179 : tx_arbitrator.vhd(356) | Found 32 by 32 bit equality operator ('==') tx_arbitrator_inst.less_than\.un6_timestamp_valid (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl))
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.rx_buffer_fsm(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_5(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_7(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_3(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_1(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_4(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_0(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_6(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_2(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.tx_arbitrator_fsm(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N:MF179 : bit_filter.vhd(130) | Found 29 by 29 bit equality operator ('==') gen_filt_pos\.valid (in view: ctu_can_fd_rtl.bit_filter_29_true_can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl))
Encoding state machine protocol_control_inst.protocol_control_fsm_inst.curr_state[0:37] (in view: ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl))
original code -> new code
   00000000000000000000000000000000000001 -> 00000000000000000000000000000000000001
   00000000000000000000000000000000000010 -> 00000000000000000000000000000000000010
   00000000000000000000000000000000000100 -> 00000000000000000000000000000000000100
   00000000000000000000000000000000001000 -> 00000000000000000000000000000000001000
   00000000000000000000000000000000010000 -> 00000000000000000000000000000000010000
   00000000000000000000000000000000100000 -> 00000000000000000000000000000000100000
   00000000000000000000000000000001000000 -> 00000000000000000000000000000001000000
   00000000000000000000000000000010000000 -> 00000000000000000000000000000010000000
   00000000000000000000000000000100000000 -> 00000000000000000000000000000100000000
   00000000000000000000000000001000000000 -> 00000000000000000000000000001000000000
   00000000000000000000000000010000000000 -> 00000000000000000000000000010000000000
   00000000000000000000000000100000000000 -> 00000000000000000000000000100000000000
   00000000000000000000000001000000000000 -> 00000000000000000000000001000000000000
   00000000000000000000000010000000000000 -> 00000000000000000000000010000000000000
   00000000000000000000000100000000000000 -> 00000000000000000000000100000000000000
   00000000000000000000001000000000000000 -> 00000000000000000000001000000000000000
   00000000000000000000010000000000000000 -> 00000000000000000000010000000000000000
   00000000000000000000100000000000000000 -> 00000000000000000000100000000000000000
   00000000000000000001000000000000000000 -> 00000000000000000001000000000000000000
   00000000000000000010000000000000000000 -> 00000000000000000010000000000000000000
   00000000000000000100000000000000000000 -> 00000000000000000100000000000000000000
   00000000000000001000000000000000000000 -> 00000000000000001000000000000000000000
   00000000000000010000000000000000000000 -> 00000000000000010000000000000000000000
   00000000000000100000000000000000000000 -> 00000000000000100000000000000000000000
   00000000000001000000000000000000000000 -> 00000000000001000000000000000000000000
   00000000000010000000000000000000000000 -> 00000000000010000000000000000000000000
   00000000000100000000000000000000000000 -> 00000000000100000000000000000000000000
   00000000001000000000000000000000000000 -> 00000000001000000000000000000000000000
   00000000010000000000000000000000000000 -> 00000000010000000000000000000000000000
   00000000100000000000000000000000000000 -> 00000000100000000000000000000000000000
   00000001000000000000000000000000000000 -> 00000001000000000000000000000000000000
   00000010000000000000000000000000000000 -> 00000010000000000000000000000000000000
   00000100000000000000000000000000000000 -> 00000100000000000000000000000000000000
   00001000000000000000000000000000000000 -> 00001000000000000000000000000000000000
   00010000000000000000000000000000000000 -> 00010000000000000000000000000000000000
   00100000000000000000000000000000000000 -> 00100000000000000000000000000000000000
   01000000000000000000000000000000000000 -> 01000000000000000000000000000000000000
   10000000000000000000000000000000000000 -> 10000000000000000000000000000000000000
Encoding state machine protocol_control_inst.protocol_control_fsm_inst.sp_control_q_i[0:2] (in view: ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine operation_control_inst.curr_state[0:3] (in view: ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : operation_control.vhd(227) | There are no possible illegal states for state machine operation_control_inst.curr_state[0:3] (in view: ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl)); safe FSM implementation is not required.
Encoding state machine fault_confinement_inst.fault_confinement_fsm_inst.curr_state[0:2] (in view: ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:MO231 : bit_time_counters.vhd(192) | Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_1(rtl) instance tq_counter_q[7:0] 
@N:MO231 : bit_time_counters.vhd(223) | Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_1(rtl) instance segm_counter_q[8:0] 
@N:MO231 : bit_time_counters.vhd(192) | Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_0(rtl) instance tq_counter_q[7:0] 
@N:MO231 : bit_time_counters.vhd(223) | Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_0(rtl) instance segm_counter_q[8:0] 
Encoding state machine current_state[0:2] (in view: ctu_can_fd_rtl.bit_time_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:MF135 : tx_data_cache.vhd(189) | RAM tx_data_cache_inst.tx_cache (in view: ctu_can_fd_rtl.bus_sampling_255_8_7_8_true_15(rtl)) is 8 words by 1 bits.
@N:MO231 : ssp_generator.vhd(213) | Found counter in view:ctu_can_fd_rtl.ssp_generator_15(rtl) instance btmc_q[14:0] 

Starting factoring (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 337MB peak: 337MB)


Finished factoring (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:12s; Memory used current: 386MB peak: 386MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:20s; Memory used current: 444MB peak: 444MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:24s; Memory used current: 444MB peak: 444MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:36s; Memory used current: 444MB peak: 444MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:38s; CPU Time elapsed 0h:00m:37s; Memory used current: 444MB peak: 444MB)


Finished preparing to map (Real Time elapsed 0h:00m:43s; CPU Time elapsed 0h:00m:41s; Memory used current: 444MB peak: 444MB)


Finished technology mapping (Real Time elapsed 0h:00m:46s; CPU Time elapsed 0h:00m:45s; Memory used current: 453MB peak: 453MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:47s		    -2.63ns		17401 /     11520
   2		0h:00m:48s		    -2.32ns		16853 /     11520
   3		0h:00m:48s		    -2.32ns		16851 /     11520
   4		0h:00m:48s		    -2.28ns		16851 /     11520
   5		0h:00m:48s		    -2.28ns		16851 /     11520
   6		0h:00m:48s		    -2.28ns		16851 /     11520
   7		0h:00m:49s		    -2.28ns		16851 /     11520
   8		0h:00m:49s		    -2.28ns		16851 /     11520
@N:FX271 : memory_registers.vhd(1152) | Replicating instance memory_registers_inst.txtb_sw_cmd\.set_abt (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 32 loads 2 times to improve timing.
@N:FX271 : bit_time_fsm.vhd(208) | Replicating instance prescaler_inst.bit_time_fsm_inst.current_state[0] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 31 loads 2 times to improve timing.
@N:FX271 : memory_reg.vhd(170) | Replicating instance memory_registers_inst.control_registers_reg_map_comp.mode_reg_comp.reg_value_r[10] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 35 loads 3 times to improve timing.
Timing driven replication report
Added 7 Registers via timing driven replication
Added 4 LUTs via timing driven replication

   9		0h:00m:54s		    -1.58ns		16878 /     11527
  10		0h:00m:54s		    -1.26ns		16881 /     11527
  11		0h:00m:55s		    -1.26ns		16881 /     11527
@N:FX271 : memory_reg.vhd(170) | Replicating instance memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[14] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) with 13 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication


  12		0h:00m:57s		    -1.25ns		16877 /     11528
  13		0h:00m:57s		    -1.03ns		16879 /     11528
  14		0h:00m:57s		    -0.94ns		16880 /     11528
  15		0h:00m:57s		    -0.85ns		16883 /     11528
  16		0h:00m:58s		    -0.72ns		16885 /     11528

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:01m:04s; CPU Time elapsed 0h:01m:03s; Memory used current: 453MB peak: 453MB)


Finished restoring hierarchy (Real Time elapsed 0h:01m:06s; CPU Time elapsed 0h:01m:04s; Memory used current: 463MB peak: 463MB)


Finished mapping can_top_level_128_8_true_true_true_true_true_true_true_63_true_1
Multiprocessing finished at : Mon Jul 18 09:36:35 2022
Multiprocessing took 0h:01m:09s realtime, 0h:01m:08s cputime

Summary of Compile Points :
*************************** 
Name                                                                 Status        Reason             Start Time                   End Time                     Realtime       CPU Time       Fast Synthesis
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
inf_ram_wrapper_32_128_12_true_true                                  Unchanged     -                  Mon Jul 18 09:06:25 2022     Mon Jul 18 09:07:00 2022     0h:00m:35s     0h:00m:33s     No            
can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0            Unchanged     -                  Mon Jul 18 09:06:28 2022     Mon Jul 18 09:06:55 2022     0h:00m:26s     0h:00m:23s     No            
can_top_level_128_8_true_true_true_true_true_true_true_63_true_1     Remapped      Design changed     Mon Jul 18 09:35:27 2022     Mon Jul 18 09:36:35 2022     0h:01m:07s     0h:01m:06s     No            
ctu_can_fd_libero_top                                                Unchanged     -                  Mon Jul 18 09:06:30 2022     Mon Jul 18 09:06:34 2022     0h:00m:03s     0h:00m:03s     No            
============================================================================================================================================================================================================
Total number of compile points: 4
===================================

Links to Compile point Reports:
******************************
Linked File:  can_top_level_128_8_true_true_true_true_true_true_true_63_true_1.srr
Linked File:  ctu_can_fd_libero_top.srr
Linked File:  can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0.srr
Linked File:  inf_ram_wrapper_32_128_12_true_true.srr

==============================


Start loading CP mapped netlist (Real Time elapsed 0h:01m:10s; CPU Time elapsed 0h:01m:09s; Memory used current: 377MB peak: 377MB)


Finished loading CP mapped netlist (Real Time elapsed 0h:01m:12s; CPU Time elapsed 0h:01m:10s; Memory used current: 393MB peak: 393MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 11541 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

================================================ Non-Gated/Non-Generated Clocks =================================================
Clock Tree ID     Driving Element     Drive Element Type           Fanout     Sample Instance                                    
---------------------------------------------------------------------------------------------------------------------------------
ClockId0001        clk_sys             clock definition on port     11541      can_top_level_inst.frame_filters_inst.ident_valid_q
=================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:01m:13s; CPU Time elapsed 0h:01m:12s; Memory used current: 394MB peak: 394MB)

Writing Analyst data base /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/synwork/ctu_can_fd_libero_top_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:01m:17s; CPU Time elapsed 0h:01m:15s; Memory used current: 394MB peak: 394MB)

Writing Verilog Simulation files
@W:BW110 :  | Renaming port dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1 due to collision with Verilog/ System Verilog reserved word  
    int --> int_Z
@W:BW110 :  | Renaming port int_manager_12_8 due to collision with Verilog/ System Verilog reserved word  
    int --> int_Z
@W:BW110 : can_top_level.vhd(103) | Renaming port can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 due to collision with Verilog/ System Verilog reserved word 
    int --> int_Z
@W:BW110 : ctu_can_fd_libero_top.vhd(90) | Renaming port ctu_can_fd_libero_top due to collision with Verilog/ System Verilog reserved word 
    int --> int_Z
@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:01m:25s; CPU Time elapsed 0h:01m:23s; Memory used current: 394MB peak: 394MB)


Finished Writing Netlists (Real Time elapsed 0h:01m:25s; CPU Time elapsed 0h:01m:23s; Memory used current: 394MB peak: 394MB)


Start final timing analysis (Real Time elapsed 0h:01m:26s; CPU Time elapsed 0h:01m:24s; Memory used current: 394MB peak: 394MB)

@N:MT615 :  | Found clock SYS_CLK with period 10.00ns  


##### START OF TIMING REPORT #####[
# Timing report written on Mon Jul 18 09:36:51 2022
#


Top view:               ctu_can_fd_libero_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/designer/ctu_can_fd_libero_top/synthesis.fdc
                       /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/constraint/ctu_can_fd_top.fdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -0.056

                   Requested     Estimated     Requested     Estimated                Clock        Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
-------------------------------------------------------------------------------------------------------------------
SYS_CLK            100.0 MHz     99.4 MHz      10.000        10.056        -0.056     declared     default_clkgroup
===================================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
SYS_CLK   SYS_CLK  |  10.000      -0.056  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: SYS_CLK
====================================



Starting Points with Worst Slack
********************************

                                                                                                                Starting                                                Arrival           
Instance                                                                                                        Reference     Type     Pin     Net                      Time        Slack 
                                                                                                                Clock                                                                     
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[8]      SYS_CLK       SLE      Q       txtb_sw_cmd_index[0]     0.218       -0.056
can_top_level_inst.memory_registers_inst.txtb_sw_cmd\.set_abt_fast                                              SYS_CLK       SLE      Q       set_abt_fast             0.218       -0.047
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.mode_reg_comp.reg_value_r_fast[10]      SYS_CLK       SLE      Q       drv_bus_fast[475]        0.218       -0.028
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.curr_state[6]                       SYS_CLK       SLE      Q       curr_state[6]            0.218       -0.025
can_top_level_inst.txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_fsm_inst.curr_state[6]                       SYS_CLK       SLE      Q       curr_state[6]            0.218       -0.012
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_priority_reg_comp.reg_value_r[0]     SYS_CLK       SLE      Q       txtb_prorities_0[0]      0.201       0.074 
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.mode_reg_comp.reg_value_r_10_rep1       SYS_CLK       SLE      Q       drv_bus_475_rep1         0.218       0.084 
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_priority_reg_comp.reg_value_r[4]     SYS_CLK       SLE      Q       txtb_prorities_1[0]      0.218       0.091 
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_priority_reg_comp.reg_value_r[8]     SYS_CLK       SLE      Q       txtb_prorities_2[0]      0.201       0.151 
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_priority_reg_comp.reg_value_r[1]     SYS_CLK       SLE      Q       txtb_prorities_0[1]      0.218       0.156 
==========================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                              Starting                                                   Required           
Instance                                                                                      Reference     Type     Pin     Net                         Time         Slack 
                                                                                              Clock                                                                         
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q                 SYS_CLK       SLE      D       N_100_i                     10.000       -0.056
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.curr_state[5]                    SYS_CLK       SLE      D       N_81_i                      10.000       0.045 
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.curr_state[2]                    SYS_CLK       SLE      D       N_87_i                      10.000       0.173 
can_top_level_inst.tx_arbitrator_inst.txtb_pointer_meta_q[0]                                  SYS_CLK       SLE      EN      un1_load_ts_lw_addr_1_i     9.873        0.591 
can_top_level_inst.tx_arbitrator_inst.txtb_pointer_meta_q[1]                                  SYS_CLK       SLE      EN      un1_load_ts_lw_addr_1_i     9.873        0.591 
can_top_level_inst.tx_arbitrator_inst.txtb_pointer_meta_q[2]                                  SYS_CLK       SLE      EN      un1_load_ts_lw_addr_1_i     9.873        0.591 
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.curr_state[1]     SYS_CLK       SLE      D       curr_state_ns[6]            10.000       0.679 
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.curr_state[5]     SYS_CLK       SLE      D       curr_state_ns[2]            10.000       0.794 
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.curr_state[6]     SYS_CLK       SLE      D       curr_state_ns[1]            10.000       0.794 
can_top_level_inst.can_core_inst.can_crc_inst.crc_calc_15_inst.crc_q[0]                       SYS_CLK       SLE      EN      un6_crc_ce                  9.873        0.802 
============================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.000

    - Propagation time:                      10.056
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.056

    Number of logic level(s):                24
    Starting point:                          can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[8] / Q
    Ending point:                            can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q / D
    The start point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
    The end   point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK

Instance / Net                                                                                                          Pin      Pin               Arrival      No. of    
Name                                                                                                           Type     Name     Dir     Delay     Time         Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[8]     SLE      Q        Out     0.218     0.218 r      -         
txtb_sw_cmd_index[0]                                                                                           Net      -        -       0.637     -            9         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i              CFG3     B        In      -         0.855 r      -         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i              CFG3     Y        Out     0.083     0.938 r      -         
N_129                                                                                                          Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                     CFG4     D        In      -         1.485 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                     CFG4     Y        Out     0.212     1.697 f      -         
un1_l1_prio_06_i                                                                                               Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux       ARI1     B        In      -         2.291 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux       ARI1     Y        Out     0.207     2.498 r      -         
l2_prio_02_m_3_1_0_y0                                                                                          Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0       ARI1     A        In      -         2.616 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0       ARI1     Y        Out     0.126     2.742 f      -         
l2_prio_02                                                                                                     Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                     CFG4     D        In      -         2.860 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                     CFG4     Y        Out     0.232     3.092 r      -         
un1_l2_prio_06_i                                                                                               Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                        ARI1     B        In      -         3.686 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                        ARI1     Y        Out     0.207     3.893 r      -         
un10_l3_winner_m_3_1_0_y0                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                      ARI1     A        In      -         4.011 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                      ARI1     Y        Out     0.126     4.137 r      -         
un10_l3_winner_i                                                                                               Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4             CFG4     D        In      -         4.684 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4             CFG4     Y        Out     0.232     4.915 r      -         
select_buf_index[1]                                                                                            Net      -        -       0.650     -            10        
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                                CFG3     B        In      -         5.565 r      -         
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                                CFG3     Y        Out     0.083     5.648 r      -         
txtb_index_muxed[1]                                                                                            Net      -        -       1.103     -            135       
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_0_wmux[12]                                             ARI1     B        In      -         6.751 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_0_wmux[12]                                             ARI1     Y        Out     0.207     6.958 r      -         
tran_word_m_3_2_1_0_y0[12]                                                                                     Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_wmux_0[12]                                             ARI1     A        In      -         7.077 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_wmux_0[12]                                             ARI1     Y        Out     0.126     7.202 r      -         
tran_word_m_3_2_1_0_y1[12]                                                                                     Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_wmux_3[12]                                             ARI1     B        In      -         7.320 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_wmux_3[12]                                             ARI1     Y        Out     0.207     7.527 r      -         
tran_word[12]                                                                                                  Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                    ARI1     D        In      -         8.122 r      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                    ARI1     FCO      Out     0.492     8.614 f      -         
un6_timestamp_valid_0_data_tmp[6]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                    ARI1     FCI      In      -         8.614 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                    ARI1     FCO      Out     0.008     8.622 f      -         
un6_timestamp_valid_0_data_tmp[7]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                    ARI1     FCI      In      -         8.622 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                    ARI1     FCO      Out     0.008     8.630 f      -         
un6_timestamp_valid_0_data_tmp[8]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                    ARI1     FCI      In      -         8.630 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                    ARI1     FCO      Out     0.008     8.638 f      -         
un6_timestamp_valid_0_data_tmp[9]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                    ARI1     FCI      In      -         8.638 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                    ARI1     FCO      Out     0.008     8.646 f      -         
un6_timestamp_valid_0_data_tmp[10]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                    ARI1     FCI      In      -         8.646 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                    ARI1     FCO      Out     0.008     8.654 f      -         
un6_timestamp_valid_0_data_tmp[11]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                    ARI1     FCI      In      -         8.654 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                    ARI1     FCO      Out     0.008     8.662 f      -         
un6_timestamp_valid_0_data_tmp[12]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                    ARI1     FCI      In      -         8.662 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                    ARI1     FCO      Out     0.008     8.670 f      -         
un6_timestamp_valid_0_data_tmp[13]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                    ARI1     FCI      In      -         8.670 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                    ARI1     FCO      Out     0.008     8.678 f      -         
un6_timestamp_valid_0_data_tmp[14]                                                                             Net      -        -       0.124     -            2         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                    CFG3     A        In      -         8.802 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                    CFG3     Y        Out     0.048     8.849 f      -         
un6_timestamp_valid_0_data_tmp[15]                                                                             Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                            CFG4     D        In      -         9.396 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                            CFG4     Y        Out     0.192     9.588 f      -         
N_100_i_1                                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                              CFG4     D        In      -         9.706 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                              CFG4     Y        Out     0.232     9.938 r      -         
N_100_i                                                                                                        Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q                                  SLE      D        In      -         10.056 r     -         
==========================================================================================================================================================================
Total path delay (propagation time + setup) of 10.056 is 3.292(32.7%) logic and 6.764(67.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.000

    - Propagation time:                      10.050
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.050

    Number of logic level(s):                30
    Starting point:                          can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[8] / Q
    Ending point:                            can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q / D
    The start point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
    The end   point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK

Instance / Net                                                                                                          Pin      Pin               Arrival      No. of    
Name                                                                                                           Type     Name     Dir     Delay     Time         Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[8]     SLE      Q        Out     0.218     0.218 r      -         
txtb_sw_cmd_index[0]                                                                                           Net      -        -       0.637     -            9         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i              CFG3     B        In      -         0.855 r      -         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i              CFG3     Y        Out     0.083     0.938 r      -         
N_129                                                                                                          Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                     CFG4     D        In      -         1.485 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                     CFG4     Y        Out     0.212     1.697 f      -         
un1_l1_prio_06_i                                                                                               Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux       ARI1     B        In      -         2.291 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux       ARI1     Y        Out     0.207     2.498 r      -         
l2_prio_02_m_3_1_0_y0                                                                                          Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0       ARI1     A        In      -         2.616 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0       ARI1     Y        Out     0.126     2.742 f      -         
l2_prio_02                                                                                                     Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                     CFG4     D        In      -         2.860 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                     CFG4     Y        Out     0.232     3.092 r      -         
un1_l2_prio_06_i                                                                                               Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                        ARI1     B        In      -         3.686 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                        ARI1     Y        Out     0.207     3.893 r      -         
un10_l3_winner_m_3_1_0_y0                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                      ARI1     A        In      -         4.011 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                      ARI1     Y        Out     0.126     4.137 r      -         
un10_l3_winner_i                                                                                               Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4             CFG4     D        In      -         4.684 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4             CFG4     Y        Out     0.232     4.915 r      -         
select_buf_index[1]                                                                                            Net      -        -       0.650     -            10        
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                                CFG3     B        In      -         5.565 r      -         
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                                CFG3     Y        Out     0.083     5.648 r      -         
txtb_index_muxed[1]                                                                                            Net      -        -       1.103     -            135       
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux[0]                                                ARI1     B        In      -         6.751 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux[0]                                                ARI1     Y        Out     0.207     6.958 r      -         
tran_word_m_3_1_1_y0[0]                                                                                        Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux_0[0]                                              ARI1     A        In      -         7.077 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux_0[0]                                              ARI1     Y        Out     0.126     7.202 r      -         
tran_word_m_3_1_1_wmux_0_Y[0]                                                                                  Net      -        -       0.124     -            2         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_0_wmux_0_RNIQBAP[0]                                      CFG3     C        In      -         7.326 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_0_wmux_0_RNIQBAP[0]                                      CFG3     Y        Out     0.148     7.474 r      -         
tran_word[0]                                                                                                   Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_1                                     ARI1     D        In      -         8.068 r      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_1                                     ARI1     FCO      Out     0.492     8.560 f      -         
un6_timestamp_valid_0_data_tmp[0]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_9                                     ARI1     FCI      In      -         8.560 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_9                                     ARI1     FCO      Out     0.008     8.568 f      -         
un6_timestamp_valid_0_data_tmp[1]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_15                                    ARI1     FCI      In      -         8.568 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_15                                    ARI1     FCO      Out     0.008     8.576 f      -         
un6_timestamp_valid_0_data_tmp[2]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_51                                    ARI1     FCI      In      -         8.576 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_51                                    ARI1     FCO      Out     0.008     8.584 f      -         
un6_timestamp_valid_0_data_tmp[3]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_75                                    ARI1     FCI      In      -         8.584 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_75                                    ARI1     FCO      Out     0.008     8.592 f      -         
un6_timestamp_valid_0_data_tmp[4]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_33                                    ARI1     FCI      In      -         8.592 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_33                                    ARI1     FCO      Out     0.008     8.600 f      -         
un6_timestamp_valid_0_data_tmp[5]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                    ARI1     FCI      In      -         8.600 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                    ARI1     FCO      Out     0.008     8.608 f      -         
un6_timestamp_valid_0_data_tmp[6]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                    ARI1     FCI      In      -         8.608 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                    ARI1     FCO      Out     0.008     8.616 f      -         
un6_timestamp_valid_0_data_tmp[7]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                    ARI1     FCI      In      -         8.616 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                    ARI1     FCO      Out     0.008     8.624 f      -         
un6_timestamp_valid_0_data_tmp[8]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                    ARI1     FCI      In      -         8.624 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                    ARI1     FCO      Out     0.008     8.632 f      -         
un6_timestamp_valid_0_data_tmp[9]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                    ARI1     FCI      In      -         8.632 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                    ARI1     FCO      Out     0.008     8.640 f      -         
un6_timestamp_valid_0_data_tmp[10]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                    ARI1     FCI      In      -         8.640 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                    ARI1     FCO      Out     0.008     8.648 f      -         
un6_timestamp_valid_0_data_tmp[11]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                    ARI1     FCI      In      -         8.648 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                    ARI1     FCO      Out     0.008     8.656 f      -         
un6_timestamp_valid_0_data_tmp[12]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                    ARI1     FCI      In      -         8.656 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                    ARI1     FCO      Out     0.008     8.664 f      -         
un6_timestamp_valid_0_data_tmp[13]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                    ARI1     FCI      In      -         8.664 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                    ARI1     FCO      Out     0.008     8.672 f      -         
un6_timestamp_valid_0_data_tmp[14]                                                                             Net      -        -       0.124     -            2         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                    CFG3     A        In      -         8.796 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                    CFG3     Y        Out     0.048     8.844 f      -         
un6_timestamp_valid_0_data_tmp[15]                                                                             Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                            CFG4     D        In      -         9.391 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                            CFG4     Y        Out     0.192     9.582 f      -         
N_100_i_1                                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                              CFG4     D        In      -         9.700 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                              CFG4     Y        Out     0.232     9.932 r      -         
N_100_i                                                                                                        Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q                                  SLE      D        In      -         10.050 r     -         
==========================================================================================================================================================================
Total path delay (propagation time + setup) of 10.050 is 3.281(32.6%) logic and 6.769(67.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.000

    - Propagation time:                      10.047
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.047

    Number of logic level(s):                24
    Starting point:                          can_top_level_inst.memory_registers_inst.txtb_sw_cmd\.set_abt_fast / Q
    Ending point:                            can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q / D
    The start point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
    The end   point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK

Instance / Net                                                                                                        Pin      Pin               Arrival      No. of    
Name                                                                                                         Type     Name     Dir     Delay     Time         Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
can_top_level_inst.memory_registers_inst.txtb_sw_cmd\.set_abt_fast                                           SLE      Q        Out     0.218     0.218 r      -         
set_abt_fast                                                                                                 Net      -        -       0.563     -            4         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i            CFG3     C        In      -         0.782 r      -         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i            CFG3     Y        Out     0.148     0.929 r      -         
N_129                                                                                                        Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                   CFG4     D        In      -         1.476 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                   CFG4     Y        Out     0.212     1.688 f      -         
un1_l1_prio_06_i                                                                                             Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux     ARI1     B        In      -         2.283 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux     ARI1     Y        Out     0.207     2.490 r      -         
l2_prio_02_m_3_1_0_y0                                                                                        Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0     ARI1     A        In      -         2.608 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0     ARI1     Y        Out     0.126     2.733 f      -         
l2_prio_02                                                                                                   Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                   CFG4     D        In      -         2.852 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                   CFG4     Y        Out     0.232     3.083 r      -         
un1_l2_prio_06_i                                                                                             Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                      ARI1     B        In      -         3.678 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                      ARI1     Y        Out     0.207     3.885 r      -         
un10_l3_winner_m_3_1_0_y0                                                                                    Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                    ARI1     A        In      -         4.003 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                    ARI1     Y        Out     0.126     4.128 r      -         
un10_l3_winner_i                                                                                             Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4           CFG4     D        In      -         4.675 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4           CFG4     Y        Out     0.232     4.907 r      -         
select_buf_index[1]                                                                                          Net      -        -       0.650     -            10        
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                              CFG3     B        In      -         5.557 r      -         
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                              CFG3     Y        Out     0.083     5.640 r      -         
txtb_index_muxed[1]                                                                                          Net      -        -       1.103     -            135       
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_0_wmux[12]                                           ARI1     B        In      -         6.743 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_0_wmux[12]                                           ARI1     Y        Out     0.207     6.950 r      -         
tran_word_m_3_2_1_0_y0[12]                                                                                   Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_wmux_0[12]                                           ARI1     A        In      -         7.068 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_wmux_0[12]                                           ARI1     Y        Out     0.126     7.194 r      -         
tran_word_m_3_2_1_0_y1[12]                                                                                   Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_wmux_3[12]                                           ARI1     B        In      -         7.312 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_2_1_wmux_3[12]                                           ARI1     Y        Out     0.207     7.519 r      -         
tran_word[12]                                                                                                Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                  ARI1     D        In      -         8.113 r      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                  ARI1     FCO      Out     0.492     8.605 f      -         
un6_timestamp_valid_0_data_tmp[6]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                  ARI1     FCI      In      -         8.605 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                  ARI1     FCO      Out     0.008     8.613 f      -         
un6_timestamp_valid_0_data_tmp[7]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                  ARI1     FCI      In      -         8.613 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                  ARI1     FCO      Out     0.008     8.621 f      -         
un6_timestamp_valid_0_data_tmp[8]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                  ARI1     FCI      In      -         8.621 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                  ARI1     FCO      Out     0.008     8.629 f      -         
un6_timestamp_valid_0_data_tmp[9]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                  ARI1     FCI      In      -         8.629 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                  ARI1     FCO      Out     0.008     8.637 f      -         
un6_timestamp_valid_0_data_tmp[10]                                                                           Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                  ARI1     FCI      In      -         8.637 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                  ARI1     FCO      Out     0.008     8.645 f      -         
un6_timestamp_valid_0_data_tmp[11]                                                                           Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                  ARI1     FCI      In      -         8.645 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                  ARI1     FCO      Out     0.008     8.653 f      -         
un6_timestamp_valid_0_data_tmp[12]                                                                           Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                  ARI1     FCI      In      -         8.653 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                  ARI1     FCO      Out     0.008     8.661 f      -         
un6_timestamp_valid_0_data_tmp[13]                                                                           Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                  ARI1     FCI      In      -         8.661 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                  ARI1     FCO      Out     0.008     8.669 f      -         
un6_timestamp_valid_0_data_tmp[14]                                                                           Net      -        -       0.124     -            2         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                  CFG3     A        In      -         8.793 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                  CFG3     Y        Out     0.048     8.841 f      -         
un6_timestamp_valid_0_data_tmp[15]                                                                           Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                          CFG4     D        In      -         9.388 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                          CFG4     Y        Out     0.192     9.579 f      -         
N_100_i_1                                                                                                    Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                            CFG4     D        In      -         9.697 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                            CFG4     Y        Out     0.232     9.929 r      -         
N_100_i                                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q                                SLE      D        In      -         10.047 r     -         
========================================================================================================================================================================
Total path delay (propagation time + setup) of 10.047 is 3.357(33.4%) logic and 6.690(66.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.000

    - Propagation time:                      10.042
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.042

    Number of logic level(s):                29
    Starting point:                          can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[8] / Q
    Ending point:                            can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q / D
    The start point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
    The end   point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK

Instance / Net                                                                                                          Pin      Pin               Arrival      No. of    
Name                                                                                                           Type     Name     Dir     Delay     Time         Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
can_top_level_inst.memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[8]     SLE      Q        Out     0.218     0.218 r      -         
txtb_sw_cmd_index[0]                                                                                           Net      -        -       0.637     -            9         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i              CFG3     B        In      -         0.855 r      -         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i              CFG3     Y        Out     0.083     0.938 r      -         
N_129                                                                                                          Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                     CFG4     D        In      -         1.485 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                     CFG4     Y        Out     0.212     1.697 f      -         
un1_l1_prio_06_i                                                                                               Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux       ARI1     B        In      -         2.291 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux       ARI1     Y        Out     0.207     2.498 r      -         
l2_prio_02_m_3_1_0_y0                                                                                          Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0       ARI1     A        In      -         2.616 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0       ARI1     Y        Out     0.126     2.742 f      -         
l2_prio_02                                                                                                     Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                     CFG4     D        In      -         2.860 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                     CFG4     Y        Out     0.232     3.092 r      -         
un1_l2_prio_06_i                                                                                               Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                        ARI1     B        In      -         3.686 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                        ARI1     Y        Out     0.207     3.893 r      -         
un10_l3_winner_m_3_1_0_y0                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                      ARI1     A        In      -         4.011 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                      ARI1     Y        Out     0.126     4.137 r      -         
un10_l3_winner_i                                                                                               Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4             CFG4     D        In      -         4.684 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4             CFG4     Y        Out     0.232     4.915 r      -         
select_buf_index[1]                                                                                            Net      -        -       0.650     -            10        
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                                CFG3     B        In      -         5.565 r      -         
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                                CFG3     Y        Out     0.083     5.648 r      -         
txtb_index_muxed[1]                                                                                            Net      -        -       1.103     -            135       
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux[2]                                                ARI1     B        In      -         6.751 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux[2]                                                ARI1     Y        Out     0.207     6.958 r      -         
tran_word_m_3_1_1_y0[2]                                                                                        Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux_0[2]                                              ARI1     A        In      -         7.077 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux_0[2]                                              ARI1     Y        Out     0.126     7.202 r      -         
tran_word_m_3_1_1_wmux_0_Y[2]                                                                                  Net      -        -       0.124     -            2         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_0_wmux_0_RNIUFAP[2]                                      CFG3     C        In      -         7.326 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_0_wmux_0_RNIUFAP[2]                                      CFG3     Y        Out     0.148     7.474 r      -         
tran_word[2]                                                                                                   Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_9                                     ARI1     D        In      -         8.068 r      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_9                                     ARI1     FCO      Out     0.492     8.560 f      -         
un6_timestamp_valid_0_data_tmp[1]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_15                                    ARI1     FCI      In      -         8.560 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_15                                    ARI1     FCO      Out     0.008     8.568 f      -         
un6_timestamp_valid_0_data_tmp[2]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_51                                    ARI1     FCI      In      -         8.568 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_51                                    ARI1     FCO      Out     0.008     8.576 f      -         
un6_timestamp_valid_0_data_tmp[3]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_75                                    ARI1     FCI      In      -         8.576 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_75                                    ARI1     FCO      Out     0.008     8.584 f      -         
un6_timestamp_valid_0_data_tmp[4]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_33                                    ARI1     FCI      In      -         8.584 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_33                                    ARI1     FCO      Out     0.008     8.592 f      -         
un6_timestamp_valid_0_data_tmp[5]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                    ARI1     FCI      In      -         8.592 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                    ARI1     FCO      Out     0.008     8.600 f      -         
un6_timestamp_valid_0_data_tmp[6]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                    ARI1     FCI      In      -         8.600 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                    ARI1     FCO      Out     0.008     8.608 f      -         
un6_timestamp_valid_0_data_tmp[7]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                    ARI1     FCI      In      -         8.608 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                    ARI1     FCO      Out     0.008     8.616 f      -         
un6_timestamp_valid_0_data_tmp[8]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                    ARI1     FCI      In      -         8.616 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                    ARI1     FCO      Out     0.008     8.624 f      -         
un6_timestamp_valid_0_data_tmp[9]                                                                              Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                    ARI1     FCI      In      -         8.624 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                    ARI1     FCO      Out     0.008     8.632 f      -         
un6_timestamp_valid_0_data_tmp[10]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                    ARI1     FCI      In      -         8.632 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                    ARI1     FCO      Out     0.008     8.640 f      -         
un6_timestamp_valid_0_data_tmp[11]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                    ARI1     FCI      In      -         8.640 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                    ARI1     FCO      Out     0.008     8.648 f      -         
un6_timestamp_valid_0_data_tmp[12]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                    ARI1     FCI      In      -         8.648 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                    ARI1     FCO      Out     0.008     8.656 f      -         
un6_timestamp_valid_0_data_tmp[13]                                                                             Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                    ARI1     FCI      In      -         8.656 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                    ARI1     FCO      Out     0.008     8.664 f      -         
un6_timestamp_valid_0_data_tmp[14]                                                                             Net      -        -       0.124     -            2         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                    CFG3     A        In      -         8.788 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                    CFG3     Y        Out     0.048     8.836 f      -         
un6_timestamp_valid_0_data_tmp[15]                                                                             Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                            CFG4     D        In      -         9.383 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                            CFG4     Y        Out     0.192     9.575 f      -         
N_100_i_1                                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                              CFG4     D        In      -         9.693 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                              CFG4     Y        Out     0.232     9.924 r      -         
N_100_i                                                                                                        Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q                                  SLE      D        In      -         10.042 r     -         
==========================================================================================================================================================================
Total path delay (propagation time + setup) of 10.042 is 3.273(32.6%) logic and 6.769(67.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.000

    - Propagation time:                      10.042
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.042

    Number of logic level(s):                30
    Starting point:                          can_top_level_inst.memory_registers_inst.txtb_sw_cmd\.set_abt_fast / Q
    Ending point:                            can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q / D
    The start point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
    The end   point is clocked by            SYS_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK

Instance / Net                                                                                                        Pin      Pin               Arrival      No. of    
Name                                                                                                         Type     Name     Dir     Delay     Time         Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
can_top_level_inst.memory_registers_inst.txtb_sw_cmd\.set_abt_fast                                           SLE      Q        Out     0.218     0.218 r      -         
set_abt_fast                                                                                                 Net      -        -       0.563     -            4         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i            CFG3     C        In      -         0.782 r      -         
can_top_level_inst.txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_fsm_inst.un50_txtb_available_i            CFG3     Y        Out     0.148     0.929 r      -         
N_129                                                                                                        Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                   CFG4     D        In      -         1.476 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l1_prio_06                                   CFG4     Y        Out     0.212     1.688 f      -         
un1_l1_prio_06_i                                                                                             Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux     ARI1     B        In      -         2.283 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_0_wmux     ARI1     Y        Out     0.207     2.490 r      -         
l2_prio_02_m_3_1_0_y0                                                                                        Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0     ARI1     A        In      -         2.608 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.l2_prio_dec_proc\.0\.l2_prio_02_m_3_1_wmux_0     ARI1     Y        Out     0.126     2.733 f      -         
l2_prio_02                                                                                                   Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                   CFG4     D        In      -         2.852 f      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un1_l2_prio_06                                   CFG4     Y        Out     0.232     3.083 r      -         
un1_l2_prio_06_i                                                                                             Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                      ARI1     B        In      -         3.678 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux                      ARI1     Y        Out     0.207     3.885 r      -         
un10_l3_winner_m_3_1_0_y0                                                                                    Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                    ARI1     A        In      -         4.003 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0                    ARI1     Y        Out     0.126     4.128 r      -         
un10_l3_winner_i                                                                                             Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4           CFG4     D        In      -         4.675 r      -         
can_top_level_inst.tx_arbitrator_inst.priority_decoder_inst.un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4           CFG4     Y        Out     0.232     4.907 r      -         
select_buf_index[1]                                                                                          Net      -        -       0.650     -            10        
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                              CFG3     B        In      -         5.557 r      -         
can_top_level_inst.tx_arbitrator_inst.un4_txtb_index_muxed_i[1]                                              CFG3     Y        Out     0.083     5.640 r      -         
txtb_index_muxed[1]                                                                                          Net      -        -       1.103     -            135       
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux[0]                                              ARI1     B        In      -         6.743 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux[0]                                              ARI1     Y        Out     0.207     6.950 r      -         
tran_word_m_3_1_1_y0[0]                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux_0[0]                                            ARI1     A        In      -         7.068 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_1_wmux_0[0]                                            ARI1     Y        Out     0.126     7.194 r      -         
tran_word_m_3_1_1_wmux_0_Y[0]                                                                                Net      -        -       0.124     -            2         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_0_wmux_0_RNIQBAP[0]                                    CFG3     C        In      -         7.318 r      -         
can_top_level_inst.tx_arbitrator_inst.tran_word_m_3_1_0_wmux_0_RNIQBAP[0]                                    CFG3     Y        Out     0.148     7.466 r      -         
tran_word[0]                                                                                                 Net      -        -       0.594     -            6         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_1                                   ARI1     D        In      -         8.060 r      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_1                                   ARI1     FCO      Out     0.492     8.552 f      -         
un6_timestamp_valid_0_data_tmp[0]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_9                                   ARI1     FCI      In      -         8.552 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_9                                   ARI1     FCO      Out     0.008     8.560 f      -         
un6_timestamp_valid_0_data_tmp[1]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_15                                  ARI1     FCI      In      -         8.560 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_15                                  ARI1     FCO      Out     0.008     8.568 f      -         
un6_timestamp_valid_0_data_tmp[2]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_51                                  ARI1     FCI      In      -         8.568 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_51                                  ARI1     FCO      Out     0.008     8.576 f      -         
un6_timestamp_valid_0_data_tmp[3]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_75                                  ARI1     FCI      In      -         8.576 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_75                                  ARI1     FCO      Out     0.008     8.584 f      -         
un6_timestamp_valid_0_data_tmp[4]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_33                                  ARI1     FCI      In      -         8.584 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_33                                  ARI1     FCO      Out     0.008     8.592 f      -         
un6_timestamp_valid_0_data_tmp[5]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                  ARI1     FCI      In      -         8.592 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_39                                  ARI1     FCO      Out     0.008     8.600 f      -         
un6_timestamp_valid_0_data_tmp[6]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                  ARI1     FCI      In      -         8.600 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_27                                  ARI1     FCO      Out     0.008     8.608 f      -         
un6_timestamp_valid_0_data_tmp[7]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                  ARI1     FCI      In      -         8.608 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_93                                  ARI1     FCO      Out     0.008     8.616 f      -         
un6_timestamp_valid_0_data_tmp[8]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                  ARI1     FCI      In      -         8.616 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_57                                  ARI1     FCO      Out     0.008     8.624 f      -         
un6_timestamp_valid_0_data_tmp[9]                                                                            Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                  ARI1     FCI      In      -         8.624 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_63                                  ARI1     FCO      Out     0.008     8.632 f      -         
un6_timestamp_valid_0_data_tmp[10]                                                                           Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                  ARI1     FCI      In      -         8.632 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_21                                  ARI1     FCO      Out     0.008     8.640 f      -         
un6_timestamp_valid_0_data_tmp[11]                                                                           Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                  ARI1     FCI      In      -         8.640 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_69                                  ARI1     FCO      Out     0.008     8.648 f      -         
un6_timestamp_valid_0_data_tmp[12]                                                                           Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                  ARI1     FCI      In      -         8.648 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_81                                  ARI1     FCO      Out     0.008     8.656 f      -         
un6_timestamp_valid_0_data_tmp[13]                                                                           Net      -        -       0.000     -            1         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                  ARI1     FCI      In      -         8.656 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_87                                  ARI1     FCO      Out     0.008     8.664 f      -         
un6_timestamp_valid_0_data_tmp[14]                                                                           Net      -        -       0.124     -            2         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                  CFG3     A        In      -         8.788 f      -         
can_top_level_inst.tx_arbitrator_inst.less_than\.un6_timestamp_valid_0_I_45                                  CFG3     Y        Out     0.048     8.836 f      -         
un6_timestamp_valid_0_data_tmp[15]                                                                           Net      -        -       0.547     -            3         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                          CFG4     D        In      -         9.383 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO_0                          CFG4     Y        Out     0.192     9.574 f      -         
N_100_i_1                                                                                                    Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                            CFG4     D        In      -         9.692 f      -         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q_RNO                            CFG4     Y        Out     0.232     9.924 r      -         
N_100_i                                                                                                      Net      -        -       0.118     -            1         
can_top_level_inst.tx_arbitrator_inst.tx_arbitrator_fsm_inst.fsm_wait_state_q                                SLE      D        In      -         10.042 r     -         
========================================================================================================================================================================
Total path delay (propagation time + setup) of 10.042 is 3.346(33.3%) logic and 6.696(66.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:01m:27s; CPU Time elapsed 0h:01m:25s; Memory used current: 394MB peak: 394MB)


Finished timing report (Real Time elapsed 0h:01m:27s; CPU Time elapsed 0h:01m:25s; Memory used current: 394MB peak: 394MB)

---------------------------------------
Resource Usage Report for ctu_can_fd_libero_top 

Mapping to part: mpf300tfcg1152-1
Cell usage:
CLKINT          2 uses
CFG1           19 uses
CFG2           1045 uses
CFG3           2944 uses
CFG4           3002 uses

Carry cells:
ARI1            652 uses - used for arithmetic functions
ARI1            5582 uses - used for Wide-Mux implementation
Total ARI1      6234 uses


Sequential Cells: 
SLE            11541 uses

DSP Blocks:    0 of 924 (0%)

I/O ports: 157
I/O primitives: 151
INBUF          116 uses
OUTBUF         35 uses


Global Clock Buffers: 2

Total LUTs:    13244

Extra resources required for RAM and MACC_PA interface logic during P&R:

RAM64X12 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K20  Interface Logic : SLEs = 0; LUTs = 0;
MACC_PA     Interface Logic : SLEs = 0; LUTs = 0;
MACC_PA_BC_ROM     Interface Logic : SLEs = 0; LUTs = 0;

Total number of SLEs after P&R:  11541 + 0 + 0 + 0 = 11541;
Total number of LUTs after P&R:  13244 + 0 + 0 + 0 = 13244;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:01m:27s; CPU Time elapsed 0h:01m:25s; Memory used current: 394MB peak: 394MB)

Process took 0h:01m:27s realtime, 0h:01m:25s cputime
# Mon Jul 18 09:36:52 2022

###########################################################]