Timing Multi Corner Report Max Delay Analysis

SmartTime Version 2022.1.0.10

Microsemi Corporation - Microsemi Libero Software Release v2022.1 (Version 2022.1.0.10)

Date: Mon Jul 18 09:52:13 2022

Design ctu_can_fd_libero_top
Family PolarFire
Die MPF300TS
Package FCG1152
Temperature Range -40 - 100 C
Voltage Range 0.97 - 1.03 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions slow_lv_ht, slow_lv_lt, fast_hv_lt

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
SYS_CLK 10.000 100.000 3.447 slow_lv_ht

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain SYS_CLK

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/tx_priority_reg_comp/reg_value_r[29]:CLK can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[0]:EN 6.286 3.447 9.848 13.295 0.128 6.545 slow_lv_ht
Path 2 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/tx_priority_reg_comp/reg_value_r[29]:CLK can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[2]:EN 6.285 3.448 9.847 13.295 0.128 6.544 slow_lv_ht
Path 3 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/tx_priority_reg_comp/reg_value_r[29]:CLK can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[1]:EN 6.285 3.448 9.847 13.295 0.128 6.544 slow_lv_ht
Path 4 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/tx_priority_reg_comp/reg_value_r[24]:CLK can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[0]:EN 6.263 3.470 9.825 13.295 0.128 6.522 slow_lv_ht
Path 5 can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/tx_priority_reg_comp/reg_value_r[24]:CLK can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[1]:EN 6.262 3.471 9.824 13.295 0.128 6.521 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/tx_priority_reg_comp/reg_value_r[29]:CLK
To: can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[0]:EN
data required time 13.295
data arrival time - 9.848
slack 3.447
Data arrival time calculation
SYS_CLK 0.000 0.000
clk_sys Clock source + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.322 1.322 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.471 1.793 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.150 1.943 1 r
I_1:A net clk_sys_ibuf_Z + 0.383 2.326 r
I_1:Y cell ADLIB:GB + 0.167 2.493 9 r
I_1/U0_RGB1_RGB0:A net I_1/U0_Y + 0.424 2.917 r
I_1/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.059 2.976 1943 f
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/tx_priority_reg_comp/reg_value_r[29]:CLK net I_1/U0_RGB1_RGB0_rgb_net_1 + 0.586 3.562 r
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/tx_priority_reg_comp/reg_value_r[29]:Q cell ADLIB:SLE + 0.209 3.771 3 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_m3_1_3:A net can_top_level_inst/txtb_prorities_7[1] + 0.198 3.969 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_m3_1_3:Y cell ADLIB:CFG4 + 0.171 4.140 1 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_m3:C net can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_m3_1_2 + 0.625 4.765 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_m3:Y cell ADLIB:CFG3 + 0.073 4.838 1 f
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un1_m2_0_a2_0:D net can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_i1_mux + 0.061 4.899 f
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un1_m2_0_a2_0:Y cell ADLIB:CFG4 + 0.071 4.970 5 f
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_prio_3[0]:C net can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un1_l1_prio_36_i + 0.092 5.062 f
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_prio_3[0]:Y cell ADLIB:CFG3 + 0.071 5.133 2 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_0_1.CO2_1:D net can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/l1_prio_3_Z[0] + 0.162 5.295 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_0_1.CO2_1:Y cell ADLIB:CFG4 + 0.238 5.533 1 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_0_1.CO2:C net can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/CO2_1_0 + 0.067 5.600 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_0_1.CO2:Y cell ADLIB:CFG3 + 0.078 5.678 1 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_m_3_1_0_wmux:C net can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner0 + 0.597 6.275 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_m_3_1_0_wmux:Y cell ADLIB:CFG4A + 0.090 6.365 1 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_m_3_1_0_wmux_0:A net can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_m_3_1_0_y0 + 0.053 6.418 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_m_3_1_0_wmux_0:Y cell ADLIB:CFG4A + 0.053 6.471 3 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4:D net can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_i + 0.119 6.590 r
can_top_level_inst/tx_arbitrator_inst/priority_decoder_inst/un10_l3_winner_m_3_1_0_wmux_0_RNIOGPC4:Y cell ADLIB:CFG4 + 0.053 6.643 10 r
can_top_level_inst/tx_arbitrator_inst/un4_txtb_index_muxed_i[1]:B net can_top_level_inst/tx_arbitrator_inst/select_buf_index[1] + 0.080 6.723 r
can_top_level_inst/tx_arbitrator_inst/un4_txtb_index_muxed_i[1]:Y cell ADLIB:CFG3 + 0.053 6.776 135 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_2_1_0_wmux[23]:B net can_top_level_inst/txtb_index_muxed[1] + 0.541 7.317 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_2_1_0_wmux[23]:Y cell ADLIB:CFG4A + 0.148 7.465 1 f
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_2_1_wmux_0[23]:A net can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_2_1_0_y0[23] + 0.062 7.527 f
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_2_1_wmux_0[23]:Y cell ADLIB:CFG4A + 0.071 7.598 1 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_2_1_wmux_3[23]:B net can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_2_1_0_y1[23] + 0.138 7.736 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_2_1_wmux_3[23]:Y cell ADLIB:CFG4A + 0.135 7.871 5 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_1_0_wmux_0_RNIR4RP46[10]:B net can_top_level_inst/tran_word[23] + 0.517 8.388 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_1_0_wmux_0_RNIR4RP46[10]:P cell ADLIB:ARI1_CC + 0.094 8.482 1 f
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_1_0_wmux_0_RNIB9FT[0]_CC_2:P[8] net NET_CC_CONFIG1016 + 0.015 8.497 f
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_1_0_wmux_0_RNIB9FT[0]_CC_2:CO cell ADLIB:CC_CONFIG + 0.222 8.719 1 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_1_0_wmux_0_RNIB9FT[0]_CC_3:CI net CI_TO_CO923 + 0.000 8.719 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_1_0_wmux_0_RNIB9FT[0]_CC_3:CC[4] cell ADLIB:CC_CONFIG + 0.133 8.852 1 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_1_0_wmux_0_RNIBGHO99[10]_FCINST1:CC net NET_CC_CONFIG1051 + 0.000 8.852 r
can_top_level_inst/tx_arbitrator_inst/tran_word_m_3_1_0_wmux_0_RNIBGHO99[10]_FCINST1:CO cell ADLIB:FCEND_BUFF_CC + 0.062 8.914 2 r
can_top_level_inst/tx_arbitrator_inst/less_than.un19_timestamp_valid_axb_31_i_RNIJ9GCA9:C net can_top_level_inst/tx_arbitrator_inst/un19_timestamp_valid_cry_30 + 0.257 9.171 r
can_top_level_inst/tx_arbitrator_inst/less_than.un19_timestamp_valid_axb_31_i_RNIJ9GCA9:Y cell ADLIB:CFG3 + 0.051 9.222 1 f
can_top_level_inst/tx_arbitrator_inst/tx_arbitrator_fsm_inst/load_ts_lw_addr_i_RNI5LQHBE:A net can_top_level_inst/tx_arbitrator_inst/un1_load_ts_lw_addr_1_i_1_0 + 0.324 9.546 f
can_top_level_inst/tx_arbitrator_inst/tx_arbitrator_fsm_inst/load_ts_lw_addr_i_RNI5LQHBE:Y cell ADLIB:CFG4 + 0.091 9.637 3 r
can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[0]:EN net can_top_level_inst/tx_arbitrator_inst/un1_load_ts_lw_addr_1_i + 0.211 9.848 r
data arrival time 9.848
Data required time calculation
SYS_CLK Clock Constraint 10.000 10.000
clk_sys Clock source + 0.000 10.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 10.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.145 11.145 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.428 11.573 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.130 11.703 1 r
I_1:A net clk_sys_ibuf_Z + 0.349 12.052 r
I_1:Y cell ADLIB:GB + 0.152 12.204 9 r
I_1/U0_RGB1_RGB2:A net I_1/U0_Y + 0.383 12.587 r
I_1/U0_RGB1_RGB2:Y cell ADLIB:RGB + 0.052 12.639 2240 f
can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[0]:CLK net I_1/U0_RGB1_RGB2_rgb_net_1 + 0.497 13.136 r
clock reconvergence pessimism + 0.295 13.431
clock jitter - 0.008 13.423
can_top_level_inst/tx_arbitrator_inst/txtb_pointer_meta_q[0]:EN Library setup time ADLIB:SLE - 0.128 13.295
data required time 13.295
Operating Conditions slow_lv_ht

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 sbe[3] can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[16]:D 12.864 12.864 0.000 9.708 slow_lv_ht
Path 2 sbe[3] can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[19]:D 12.825 12.825 0.000 9.660 slow_lv_ht
Path 3 sbe[3] can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[30]:D 12.753 12.753 0.000 9.597 slow_lv_ht
Path 4 sbe[3] can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[6]:D 12.749 12.749 0.000 9.585 slow_lv_ht
Path 5 sbe[3] can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[4]:D 12.730 12.730 0.000 9.584 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: sbe[3]
To: can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[16]:D
data required time N/C
data arrival time - 12.864
slack N/C
Data arrival time calculation
sbe[3] 0.000 0.000 r
sbe_ibuf[3]/U_IOPAD:PAD net sbe[3] + 0.000 0.000 r
sbe_ibuf[3]/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.318 1.318 1 r
sbe_ibuf[3]/U_IOIN:YIN net sbe_ibuf[3]/YIN + 0.000 1.318 r
sbe_ibuf[3]/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.346 1.664 185 r
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/rx_data_access_signaller_comp/be_active:A net sbe_c[3] + 3.531 5.195 r
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/rx_data_access_signaller_comp/be_active:Y cell ADLIB:CFG4 + 0.247 5.442 1 f
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/rx_data_access_signaller_comp/access_active_0[0]:A net can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/rx_data_access_signaller_comp/be_active_Z + 0.332 5.774 f
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/rx_data_access_signaller_comp/access_active_0[0]:Y cell ADLIB:CFG3 + 0.050 5.824 1 r
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/rx_data_access_signaller_comp/access_active[0]:C net can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/rx_data_access_signaller_comp/access_active_0_Z[0] + 0.810 6.634 r
can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/rx_data_access_signaller_comp/access_active[0]:Y cell ADLIB:CFG4 + 0.053 6.687 1 r
can_top_level_inst/memory_registers_inst/drv_bus_57[352]:A net can_top_level_inst/memory_registers_inst/rx_data_read + 1.012 7.699 r
can_top_level_inst/memory_registers_inst/drv_bus_57[352]:Y cell ADLIB:CFG4 + 0.156 7.855 2 r
can_top_level_inst/rx_buffer_inst/un1_read_increment:B net can_top_level_inst/drv_bus[352] + 0.234 8.089 r
can_top_level_inst/rx_buffer_inst/un1_read_increment:Y cell ADLIB:CFG2 + 0.053 8.142 47 r
can_top_level_inst/rx_buffer_inst/RAM_read_address[5]:A net can_top_level_inst/rx_buffer_inst/un1_read_increment_i + 0.833 8.975 r
can_top_level_inst/rx_buffer_inst/RAM_read_address[5]:Y cell ADLIB:CFG3 + 0.053 9.028 2 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/port_b_address_i[5]:C net can_top_level_inst/rx_buffer_inst/RAM_read_address_Z[5] + 0.347 9.375 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/port_b_address_i[5]:Y cell ADLIB:CFG3 + 0.090 9.465 1010 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_44_1_0_wmux[16]:B net can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/port_b_address_i_Z[5] + 1.285 10.750 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_44_1_0_wmux[16]:Y cell ADLIB:CFG4A + 0.148 10.898 1 f
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_44_1_0_wmux_0[16]:A net can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_44_1_0_y0[16] + 0.071 10.969 f
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_44_1_0_wmux_0[16]:Y cell ADLIB:CFG4A + 0.071 11.040 1 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_46_2[16]:D net can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_44_1_0_wmux_0_Y[16] + 0.126 11.166 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_46_2[16]:Y cell ADLIB:CFG4 + 0.135 11.301 1 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_46[16]:B net can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/N_1457_2 + 0.409 11.710 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_46[16]:Y cell ADLIB:CFG3 + 0.053 11.763 1 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_63_2_0[16]:B net can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_46_Z[16] + 0.584 12.347 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_63_2_0[16]:Y cell ADLIB:CFG3 + 0.078 12.425 1 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_127_1_0_wmux[16]:D net can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_63_2_0_Z[16] + 0.134 12.559 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_127_1_0_wmux[16]:Y cell ADLIB:CFG4A + 0.135 12.694 1 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_127_1_0_wmux_0[16]:A net can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_127_1_0_y0[16] + 0.064 12.758 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data_127_1_0_wmux_0[16]:Y cell ADLIB:CFG4A + 0.078 12.836 1 r
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[16]:D net can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/int_read_data[16] + 0.028 12.864 r
data arrival time 12.864
Data required time calculation
SYS_CLK N/C N/C
clk_sys Clock source + 0.000 N/C r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 N/C r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.145 N/C 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.428 N/C r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.130 N/C 1 r
I_1:A net clk_sys_ibuf_Z + 0.349 N/C r
I_1:Y cell ADLIB:GB + 0.152 N/C 9 r
I_1/U0_RGB1_RGB3:A net I_1/U0_Y + 0.391 N/C r
I_1/U0_RGB1_RGB3:Y cell ADLIB:RGB + 0.052 N/C 1941 f
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[16]:CLK net I_1/U0_RGB1_RGB3_rgb_net_1 + 0.509 N/C r
clock jitter - 0.008 N/C
can_top_level_inst/rx_buffer_inst/rx_buffer_ram_inst/rx_buf_RAM_inst/data_out_Z[16]:D Library setup time ADLIB:SLE - 0.000 N/C
Operating Conditions slow_lv_ht

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 can_top_level_inst/memory_registers_inst/control_registers_cs_reg:CLK data_out[16] 9.089 12.645 12.645 slow_lv_ht
Path 2 can_top_level_inst/memory_registers_inst/control_registers_cs_reg:CLK data_out[2] 8.830 12.386 12.386 slow_lv_ht
Path 3 can_top_level_inst/memory_registers_inst/test_registers_cs_reg:CLK data_out[13] 8.472 12.028 12.028 slow_lv_ht
Path 4 can_top_level_inst/memory_registers_inst/test_registers_cs_reg:CLK data_out[25] 8.420 11.976 11.976 slow_lv_ht
Path 5 can_top_level_inst/memory_registers_inst/control_registers_cs_reg:CLK data_out[9] 8.294 11.850 11.850 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: can_top_level_inst/memory_registers_inst/control_registers_cs_reg:CLK
To: data_out[16]
data required time N/C
data arrival time - 12.645
slack N/C
Data arrival time calculation
SYS_CLK 0.000 0.000
clk_sys Clock source + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.322 1.322 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.471 1.793 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.150 1.943 1 r
I_1:A net clk_sys_ibuf_Z + 0.383 2.326 r
I_1:Y cell ADLIB:GB + 0.167 2.493 9 r
I_1/U0_RGB1_RGB0:A net I_1/U0_Y + 0.424 2.917 r
I_1/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.059 2.976 1943 f
can_top_level_inst/memory_registers_inst/control_registers_cs_reg:CLK net I_1/U0_RGB1_RGB0_rgb_net_1 + 0.580 3.556 r
can_top_level_inst/memory_registers_inst/control_registers_cs_reg:Q cell ADLIB:SLE + 0.190 3.746 32 f
can_top_level_inst/memory_registers_inst/data_out_cZ[16]:D net can_top_level_inst/memory_registers_inst/control_registers_cs_reg_Z + 1.909 5.655 f
can_top_level_inst/memory_registers_inst/data_out_cZ[16]:Y cell ADLIB:CFG4 + 0.178 5.833 1 f
data_out_obuf[16]/U_IOTRI:D net data_out_c[16] + 2.727 8.560 f
data_out_obuf[16]/U_IOTRI:DOUT cell ADLIB:IOTRI_OB_EB + 0.969 9.529 1 f
data_out_obuf[16]/U_IOPAD:D net data_out_obuf[16]/DOUT + 0.000 9.529 f
data_out_obuf[16]/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 3.116 12.645 0 f
data_out[16] net data_out[16] + 0.000 12.645 f
data arrival time 12.645
Data required time calculation
SYS_CLK N/C N/C
clk_sys Clock source + 0.000 N/C r
data_out[16] N/C f
Operating Conditions slow_lv_ht

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep:CLK can_top_level_inst/txt_buf_comp_gen.7.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[23]:ALn 4.388 5.333 7.928 13.261 0.209 4.659 0.062 slow_lv_ht
Path 2 can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep:CLK can_top_level_inst/txt_buf_comp_gen.7.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[21]:ALn 4.388 5.333 7.928 13.261 0.209 4.659 0.062 slow_lv_ht
Path 3 can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep:CLK can_top_level_inst/txt_buf_comp_gen.7.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[17]:ALn 4.388 5.333 7.928 13.261 0.209 4.659 0.062 slow_lv_ht
Path 4 can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep:CLK can_top_level_inst/txt_buf_comp_gen.0.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_12[8]:ALn 4.386 5.334 7.926 13.260 0.209 4.658 0.063 slow_lv_ht
Path 5 can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep:CLK can_top_level_inst/txt_buf_comp_gen.0.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_12[11]:ALn 4.386 5.334 7.926 13.260 0.209 4.658 0.063 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep:CLK
To: can_top_level_inst/txt_buf_comp_gen.7.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[23]:ALn
data required time 13.261
data arrival time - 7.928
slack 5.333
Data arrival time calculation
SYS_CLK 0.000 0.000
clk_sys Clock source + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 0.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.322 1.322 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.471 1.793 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.150 1.943 1 r
I_1:A net clk_sys_ibuf_Z + 0.383 2.326 r
I_1:Y cell ADLIB:GB + 0.167 2.493 9 r
I_1/U0_RGB1_RGB7:A net I_1/U0_Y + 0.429 2.922 r
I_1/U0_RGB1_RGB7:Y cell ADLIB:RGB + 0.059 2.981 1 f
can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep:CLK net I_1/U0_RGB1_RGB7_rgb_net_1 + 0.559 3.540 r
can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep:Q cell ADLIB:SLE + 0.201 3.741 1 r
can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep_RNIGSV3:A net can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep_Z + 2.934 6.675 r
can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep_RNIGSV3:Y cell ADLIB:GB + 0.129 6.804 8 r
can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep_RNIGSV3/U0_RGB1_RGB0:A net can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep_RNIGSV3/U0_Y + 0.428 7.232 r
can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep_RNIGSV3/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.059 7.291 1758 f
can_top_level_inst/txt_buf_comp_gen.7.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[23]:ALn net can_top_level_inst/memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/reg_q_rep_RNIGSV3/U0_RGB1_RGB0_rgb_net_1 + 0.637 7.928 r
data arrival time 7.928
Data required time calculation
SYS_CLK Clock Constraint 10.000 10.000
clk_sys Clock source + 0.000 10.000 r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 10.000 r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.145 11.145 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.428 11.573 r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.130 11.703 1 r
I_1:A net clk_sys_ibuf_Z + 0.349 12.052 r
I_1:Y cell ADLIB:GB + 0.152 12.204 9 r
I_1/U0_RGB1_RGB0:A net I_1/U0_Y + 0.384 12.588 r
I_1/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.052 12.640 1943 f
can_top_level_inst/txt_buf_comp_gen.7.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[23]:CLK net I_1/U0_RGB1_RGB0_rgb_net_1 + 0.543 13.183 r
clock reconvergence pessimism + 0.295 13.478
clock jitter - 0.008 13.470
can_top_level_inst/txt_buf_comp_gen.7.txt_buffer_inst/txt_buffer_ram_inst/txt_buf_ram_inst/ram_rst_true_gen.ram_write_process.ram_memory_13[23]:ALn Library recovery time ADLIB:SLE - 0.209 13.261
data required time 13.261
Operating Conditions slow_lv_ht

SET External Recovery

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) External Recovery (ns) Operating Conditions
Path 1 res_n can_top_level_inst/rst_sync_inst/rst:ALn 2.205 2.205 0.197 -0.517 slow_lv_lt
Path 2 res_n can_top_level_inst/rst_sync_inst/rff:ALn 2.205 2.205 0.197 -0.517 slow_lv_lt

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: res_n
To: can_top_level_inst/rst_sync_inst/rst:ALn
data required time N/C
data arrival time - 2.205
slack N/C
Data arrival time calculation
res_n 0.000 0.000 r
res_n_ibuf/U_IOPAD:PAD net res_n + 0.000 0.000 r
res_n_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.518 0.518 1 r
res_n_ibuf/U_IOIN:YIN net res_n_ibuf/YIN + 0.000 0.518 r
res_n_ibuf/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.274 0.792 2 r
can_top_level_inst/rst_sync_inst/rst:ALn net res_n_c + 1.413 2.205 r
data arrival time 2.205
Data required time calculation
SYS_CLK N/C N/C
clk_sys Clock source + 0.000 N/C r
clk_sys_ibuf/U_IOPAD:PAD net clk_sys + 0.000 N/C r
clk_sys_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.994 N/C 1 r
I_1/U0_IOBA:A net clk_sys_ibuf/YIN + 0.418 N/C r
I_1/U0_IOBA:Y cell ADLIB:ICB_CLKINT + 0.126 N/C 1 r
I_1:A net clk_sys_ibuf_Z + 0.325 N/C r
I_1:Y cell ADLIB:GB + 0.158 N/C 9 r
I_1/U0_RGB1_RGB0:A net I_1/U0_Y + 0.356 N/C r
I_1/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.053 N/C 1943 f
can_top_level_inst/rst_sync_inst/rst:CLK net I_1/U0_RGB1_RGB0_rgb_net_1 + 0.489 N/C r
clock jitter - 0.008 N/C
can_top_level_inst/rst_sync_inst/rst:ALn Library recovery time ADLIB:SLE - 0.197 N/C
Operating Conditions slow_lv_lt

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets