#Build: Synplify Pro (R) S-2021.09M, Build 223R, Feb 23 2022
#install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
#OS: Linux 
#Hostname: ondrej-Aspire-V3-771

# Fri Jul 15 21:02:08 2022

#Implementation: synthesis


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63093
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys HDL Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63093
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys VHDL Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 
@N: :  | stack limit increased to max 
@N: : can_top_level.vhd(103) | Top entity is set to can_top_level.
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst_ce.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_constants_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_frame_format.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_register_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_config_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/drv_stat_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/unary_ops_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/mux2.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_byte.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_preload.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sig_sync.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/access_signaler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/address_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_registers_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/cmn_reg_map_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_sync.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/parity_calculator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_types_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/id_transfer_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_destuffing.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_stuffing.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_traffic_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/crc_calc.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_crc.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_rules.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/operation_control.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/endian_swapper.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dlc_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/reintegration_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/retransmitt_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_shift_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_shift_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_core.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_err_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_edge_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trv_delay_meas.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_data_cache.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sample_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ssp_generator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_filter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/range_filter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/frame_filters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_module.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/clk_gate.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_registers_reg_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/test_registers_reg_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/priority_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_segment_meter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_generator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/segment_end_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/synchronisation_checker.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/prescaler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd'. 
VHDL syntax check successful!
@N:CD231 : std1164.vhd(889) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
@N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time.

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)


Process completed successfully.
# Fri Jul 15 21:02:09 2022

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63093
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Verilog Compiler, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/generic/acg5.v" (library work)
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/opt/microsemi/Libero_SoC_v2022.1/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/component/polarfire_syn_comps.v" (library work)
@W:CG100 : polarfire_syn_comps.v(21) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(61) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(88) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(118) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(168) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(213) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(232) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(281) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(335) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(657) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(761) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(795) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1059) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1369) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1396) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1441) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1474) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1492) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1518) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1559) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1581) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1599) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1616) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1635) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1652) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1681) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1712) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1802) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2026) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2187) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2203) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2219) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2235) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2267) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2648) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3661) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3732) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3861) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3879) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3896) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3911) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3926) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3953) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4065) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4096) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4142) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4252) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4436) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4477) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4503) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4520) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4597) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(5361) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6171) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6280) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6318) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6391) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(7280) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(8337) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(9296) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10032) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10747) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10781) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10817) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10864) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10898) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(11764) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12807) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12819) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12830) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12843) | User defined pragma syn_black_box detected

@N: :  | stack limit increased to max 
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB)


Process completed successfully.
# Fri Jul 15 21:02:09 2022

###########################################################]
###########################################################[
@N: :  | stack limit increased to max 
@N: : can_top_level.vhd(103) | Top entity is set to can_top_level.
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dff_arst_ce.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_constants_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_frame_format.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_fd_register_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_config_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/drv_stat_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/unary_ops_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/mux2.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_byte.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/shift_reg_preload.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sig_sync.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/access_signaler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/address_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_registers_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/cmn_reg_map_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_sync.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/parity_calculator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_types_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/id_transfer_pkg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_destuffing.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_stuffing.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_traffic_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/crc_calc.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_crc.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement_rules.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/fault_confinement.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/operation_control.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/endian_swapper.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/err_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/dlc_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/reintegration_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/retransmitt_counter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_shift_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_shift_reg.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/protocol_control.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_core.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_err_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/data_edge_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trv_delay_meas.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_data_cache.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/sample_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ssp_generator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bus_sampling.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_filter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/range_filter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/frame_filters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_module.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/int_manager.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/clk_gate.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/control_registers_reg_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/test_registers_reg_map.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/memory_registers.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_pointers.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer_ram.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/priority_decoder.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/tx_arbitrator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer_ram.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/txt_buffer.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_cfg_capture.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_fsm.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_segment_meter.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/bit_time_counters.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/trigger_generator.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/segment_end_detector.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/synchronisation_checker.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/prescaler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file '/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd'. 
VHDL syntax check successful!
@N:CD231 : std1164.vhd(889) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
@N:CD630 : can_top_level.vhd(103) | Synthesizing ctu_can_fd_rtl.can_top_level.rtl.
@N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time.
@N:CD630 : bus_sampling.vhd(97) | Synthesizing ctu_can_fd_rtl.bus_sampling.rtl.
@N:CD630 : sample_mux.vhd(93) | Synthesizing ctu_can_fd_rtl.sample_mux.rtl.
Post processing for ctu_can_fd_rtl.sample_mux.rtl
Running optimization stage 1 on sample_mux .......
Finished optimization stage 1 on sample_mux (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB)
@N:CD630 : bit_err_detector.vhd(95) | Synthesizing ctu_can_fd_rtl.bit_err_detector.rtl.
Post processing for ctu_can_fd_rtl.bit_err_detector.rtl
Running optimization stage 1 on bit_err_detector .......
Finished optimization stage 1 on bit_err_detector (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB)
@N:CD630 : tx_data_cache.vhd(94) | Synthesizing ctu_can_fd_rtl.tx_data_cache.rtl.
Post processing for ctu_can_fd_rtl.tx_data_cache.rtl
Running optimization stage 1 on tx_data_cache .......
Finished optimization stage 1 on tx_data_cache (CPU Time 0h:00m:00s, Memory Used current: 147MB peak: 147MB)
@N:CD630 : ssp_generator.vhd(94) | Synthesizing ctu_can_fd_rtl.ssp_generator.rtl.
Post processing for ctu_can_fd_rtl.ssp_generator.rtl
Running optimization stage 1 on ssp_generator .......
Finished optimization stage 1 on ssp_generator (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : dff_arst.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst.rtl.
Post processing for ctu_can_fd_rtl.dff_arst.rtl
Running optimization stage 1 on dff_arst .......
Finished optimization stage 1 on dff_arst (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : rst_reg.vhd(82) | Synthesizing ctu_can_fd_rtl.rst_reg.rtl.
@N:CD630 : mux2.vhd(89) | Synthesizing ctu_can_fd_rtl.mux2.rtl.
Post processing for ctu_can_fd_rtl.mux2.rtl
Running optimization stage 1 on mux2 .......
Finished optimization stage 1 on mux2 (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
Post processing for ctu_can_fd_rtl.rst_reg.rtl
Running optimization stage 1 on rst_reg .......
Finished optimization stage 1 on rst_reg (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : data_edge_detector.vhd(109) | Synthesizing ctu_can_fd_rtl.data_edge_detector.rtl.
Post processing for ctu_can_fd_rtl.data_edge_detector.rtl
Running optimization stage 1 on data_edge_detector .......
Finished optimization stage 1 on data_edge_detector (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : trv_delay_meas.vhd(142) | Synthesizing ctu_can_fd_rtl.trv_delay_measurement.rtl.
Post processing for ctu_can_fd_rtl.trv_delay_measurement.rtl
Running optimization stage 1 on trv_delay_measurement .......
Finished optimization stage 1 on trv_delay_measurement (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : sig_sync.vhd(77) | Synthesizing ctu_can_fd_rtl.sig_sync.rtl.
Post processing for ctu_can_fd_rtl.sig_sync.rtl
Running optimization stage 1 on sig_sync .......
Finished optimization stage 1 on sig_sync (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
Post processing for ctu_can_fd_rtl.bus_sampling.rtl
Running optimization stage 1 on bus_sampling .......
Finished optimization stage 1 on bus_sampling (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CD630 : prescaler.vhd(100) | Synthesizing ctu_can_fd_rtl.prescaler.rtl.
@N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time.
@N:CD630 : trigger_generator.vhd(122) | Synthesizing ctu_can_fd_rtl.trigger_generator.rtl.
Post processing for ctu_can_fd_rtl.trigger_generator.rtl
Running optimization stage 1 on trigger_generator .......
Finished optimization stage 1 on trigger_generator (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : bit_time_fsm.vhd(95) | Synthesizing ctu_can_fd_rtl.bit_time_fsm.rtl.
@N:CD233 : can_types_pkg.vhd(147) | Using sequential encoding for type t_bit_time.
Post processing for ctu_can_fd_rtl.bit_time_fsm.rtl
Running optimization stage 1 on bit_time_fsm .......
Finished optimization stage 1 on bit_time_fsm (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : segment_end_detector.vhd(96) | Synthesizing ctu_can_fd_rtl.segment_end_detector.rtl.
Post processing for ctu_can_fd_rtl.segment_end_detector.rtl
Running optimization stage 1 on segment_end_detector .......
Finished optimization stage 1 on segment_end_detector (CPU Time 0h:00m:00s, Memory Used current: 149MB peak: 149MB)
@N:CD630 : bit_time_counters.vhd(98) | Synthesizing ctu_can_fd_rtl.bit_time_counters.rtl.
Post processing for ctu_can_fd_rtl.bit_time_counters.rtl
Running optimization stage 1 on bit_time_counters .......
Finished optimization stage 1 on bit_time_counters (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 150MB)
@N:CD630 : bit_segment_meter.vhd(196) | Synthesizing ctu_can_fd_rtl.bit_segment_meter.rtl.
Post processing for ctu_can_fd_rtl.bit_segment_meter.rtl
Running optimization stage 1 on bit_segment_meter .......
Finished optimization stage 1 on bit_segment_meter (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB)
@N:CD630 : synchronisation_checker.vhd(94) | Synthesizing ctu_can_fd_rtl.synchronisation_checker.rtl.
Post processing for ctu_can_fd_rtl.synchronisation_checker.rtl
Running optimization stage 1 on synchronisation_checker .......
Finished optimization stage 1 on synchronisation_checker (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB)
@N:CD630 : bit_time_cfg_capture.vhd(96) | Synthesizing ctu_can_fd_rtl.bit_time_cfg_capture.rtl.
Post processing for ctu_can_fd_rtl.bit_time_cfg_capture.rtl
Running optimization stage 1 on bit_time_cfg_capture .......
Finished optimization stage 1 on bit_time_cfg_capture (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB)
Post processing for ctu_can_fd_rtl.prescaler.rtl
Running optimization stage 1 on prescaler .......
Finished optimization stage 1 on prescaler (CPU Time 0h:00m:00s, Memory Used current: 151MB peak: 151MB)
@N:CD630 : can_core.vhd(100) | Synthesizing ctu_can_fd_rtl.can_core.rtl.
@N:CD630 : trigger_mux.vhd(108) | Synthesizing ctu_can_fd_rtl.trigger_mux.rtl.
@N:CD630 : dff_arst_ce.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst_ce.rtl.
Post processing for ctu_can_fd_rtl.dff_arst_ce.rtl
Running optimization stage 1 on dff_arst_ce .......
Finished optimization stage 1 on dff_arst_ce (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
Post processing for ctu_can_fd_rtl.trigger_mux.rtl
Running optimization stage 1 on trigger_mux .......
Finished optimization stage 1 on trigger_mux (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
@N:CD630 : bus_traffic_counters.vhd(92) | Synthesizing ctu_can_fd_rtl.bus_traffic_counters.rtl.
Post processing for ctu_can_fd_rtl.bus_traffic_counters.rtl
Running optimization stage 1 on bus_traffic_counters .......
Finished optimization stage 1 on bus_traffic_counters (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
@N:CD630 : bit_destuffing.vhd(102) | Synthesizing ctu_can_fd_rtl.bit_destuffing.rtl.
@N:CD630 : dff_arst_ce.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst_ce.rtl.
Post processing for ctu_can_fd_rtl.dff_arst_ce.rtl
Running optimization stage 1 on dff_arst_ce .......
Finished optimization stage 1 on dff_arst_ce (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
@N:CD630 : dff_arst.vhd(77) | Synthesizing ctu_can_fd_rtl.dff_arst.rtl.
Post processing for ctu_can_fd_rtl.dff_arst.rtl
Running optimization stage 1 on dff_arst .......
Finished optimization stage 1 on dff_arst (CPU Time 0h:00m:00s, Memory Used current: 152MB peak: 152MB)
Post processing for ctu_can_fd_rtl.bit_destuffing.rtl
Running optimization stage 1 on bit_destuffing .......
Finished optimization stage 1 on bit_destuffing (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : bit_stuffing.vhd(100) | Synthesizing ctu_can_fd_rtl.bit_stuffing.rtl.
Post processing for ctu_can_fd_rtl.bit_stuffing.rtl
Running optimization stage 1 on bit_stuffing .......
Finished optimization stage 1 on bit_stuffing (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : can_crc.vhd(104) | Synthesizing ctu_can_fd_rtl.can_crc.rtl.
@N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl.
Post processing for ctu_can_fd_rtl.crc_calc.rtl
Running optimization stage 1 on crc_calc .......
Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl.
Post processing for ctu_can_fd_rtl.crc_calc.rtl
Running optimization stage 1 on crc_calc .......
Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : crc_calc.vhd(95) | Synthesizing ctu_can_fd_rtl.crc_calc.rtl.
Post processing for ctu_can_fd_rtl.crc_calc.rtl
Running optimization stage 1 on crc_calc .......
Finished optimization stage 1 on crc_calc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
Post processing for ctu_can_fd_rtl.can_crc.rtl
Running optimization stage 1 on can_crc .......
Finished optimization stage 1 on can_crc (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : fault_confinement.vhd(94) | Synthesizing ctu_can_fd_rtl.fault_confinement.rtl.
@N:CD630 : fault_confinement_rules.vhd(94) | Synthesizing ctu_can_fd_rtl.fault_confinement_rules.rtl.
Post processing for ctu_can_fd_rtl.fault_confinement_rules.rtl
Running optimization stage 1 on fault_confinement_rules .......
Finished optimization stage 1 on fault_confinement_rules (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : err_counters.vhd(100) | Synthesizing ctu_can_fd_rtl.err_counters.rtl.
Post processing for ctu_can_fd_rtl.err_counters.rtl
Running optimization stage 1 on err_counters .......
Finished optimization stage 1 on err_counters (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CD630 : fault_confinement_fsm.vhd(96) | Synthesizing ctu_can_fd_rtl.fault_confinement_fsm.rtl.
@N:CD233 : can_types_pkg.vhd(91) | Using sequential encoding for type t_fault_conf_state.
Post processing for ctu_can_fd_rtl.fault_confinement_fsm.rtl
Running optimization stage 1 on fault_confinement_fsm .......
Finished optimization stage 1 on fault_confinement_fsm (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
Post processing for ctu_can_fd_rtl.fault_confinement.rtl
Running optimization stage 1 on fault_confinement .......
Finished optimization stage 1 on fault_confinement (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
@N:CD630 : operation_control.vhd(93) | Synthesizing ctu_can_fd_rtl.operation_control.rtl.
@N:CD233 : can_types_pkg.vhd(98) | Using sequential encoding for type t_operation_control_state.
Post processing for ctu_can_fd_rtl.operation_control.rtl
Running optimization stage 1 on operation_control .......
Finished optimization stage 1 on operation_control (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
@N:CD630 : protocol_control.vhd(98) | Synthesizing ctu_can_fd_rtl.protocol_control.rtl.
@N:CD630 : rx_shift_reg.vhd(98) | Synthesizing ctu_can_fd_rtl.rx_shift_reg.rtl.
@N:CD630 : shift_reg_byte.vhd(85) | Synthesizing ctu_can_fd_rtl.shift_reg_byte.rtl.
Post processing for ctu_can_fd_rtl.shift_reg_byte.rtl
Running optimization stage 1 on shift_reg_byte .......
Finished optimization stage 1 on shift_reg_byte (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
Post processing for ctu_can_fd_rtl.rx_shift_reg.rtl
Running optimization stage 1 on rx_shift_reg .......
Finished optimization stage 1 on rx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
@N:CD630 : tx_shift_reg.vhd(95) | Synthesizing ctu_can_fd_rtl.tx_shift_reg.rtl.
@N:CD630 : shift_reg_preload.vhd(77) | Synthesizing ctu_can_fd_rtl.shift_reg_preload.rtl.
Post processing for ctu_can_fd_rtl.shift_reg_preload.rtl
Running optimization stage 1 on shift_reg_preload .......
Finished optimization stage 1 on shift_reg_preload (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
Post processing for ctu_can_fd_rtl.tx_shift_reg.rtl
Running optimization stage 1 on tx_shift_reg .......
Finished optimization stage 1 on tx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : err_detector.vhd(97) | Synthesizing ctu_can_fd_rtl.err_detector.rtl.
Post processing for ctu_can_fd_rtl.err_detector.rtl
Running optimization stage 1 on err_detector .......
Finished optimization stage 1 on err_detector (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : retransmitt_counter.vhd(95) | Synthesizing ctu_can_fd_rtl.retransmitt_counter.rtl.
Post processing for ctu_can_fd_rtl.retransmitt_counter.rtl
Running optimization stage 1 on retransmitt_counter .......
Finished optimization stage 1 on retransmitt_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : reintegration_counter.vhd(93) | Synthesizing ctu_can_fd_rtl.reintegration_counter.rtl.
Post processing for ctu_can_fd_rtl.reintegration_counter.rtl
Running optimization stage 1 on reintegration_counter .......
Finished optimization stage 1 on reintegration_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : control_counter.vhd(97) | Synthesizing ctu_can_fd_rtl.control_counter.rtl.
Post processing for ctu_can_fd_rtl.control_counter.rtl
Running optimization stage 1 on control_counter .......
Finished optimization stage 1 on control_counter (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CD630 : protocol_control_fsm.vhd(110) | Synthesizing ctu_can_fd_rtl.protocol_control_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(106) | Using onehot encoding for type t_protocol_control_state. For example, enumeration s_pc_off is mapped to "10000000000000000000000000000000000000".
@N:CD630 : dlc_decoder.vhd(88) | Synthesizing ctu_can_fd_rtl.dlc_decoder.rtl.
Post processing for ctu_can_fd_rtl.dlc_decoder.rtl
Running optimization stage 1 on dlc_decoder .......
Finished optimization stage 1 on dlc_decoder (CPU Time 0h:00m:00s, Memory Used current: 158MB peak: 158MB)
Post processing for ctu_can_fd_rtl.protocol_control_fsm.rtl
Running optimization stage 1 on protocol_control_fsm .......
Finished optimization stage 1 on protocol_control_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : endian_swapper.vhd(95) | Synthesizing ctu_can_fd_rtl.endian_swapper.rtl.
Post processing for ctu_can_fd_rtl.endian_swapper.rtl
Running optimization stage 1 on endian_swapper .......
Finished optimization stage 1 on endian_swapper (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.protocol_control.rtl
Running optimization stage 1 on protocol_control .......
Finished optimization stage 1 on protocol_control (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.can_core.rtl
Running optimization stage 1 on can_core .......
Finished optimization stage 1 on can_core (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : int_manager.vhd(97) | Synthesizing ctu_can_fd_rtl.int_manager.rtl.
@N:CD630 : int_module.vhd(103) | Synthesizing ctu_can_fd_rtl.int_module.rtl.
Post processing for ctu_can_fd_rtl.int_module.rtl
Running optimization stage 1 on int_module .......
Finished optimization stage 1 on int_module (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.int_manager.rtl
Running optimization stage 1 on int_manager .......
Finished optimization stage 1 on int_manager (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : frame_filters.vhd(101) | Synthesizing ctu_can_fd_rtl.frame_filters.rtl.
@N:CD630 : range_filter.vhd(94) | Synthesizing ctu_can_fd_rtl.range_filter.rtl.
Post processing for ctu_can_fd_rtl.range_filter.rtl
Running optimization stage 1 on range_filter .......
Finished optimization stage 1 on range_filter (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : bit_filter.vhd(92) | Synthesizing ctu_can_fd_rtl.bit_filter.rtl.
Post processing for ctu_can_fd_rtl.bit_filter.rtl
Running optimization stage 1 on bit_filter .......
Finished optimization stage 1 on bit_filter (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.frame_filters.rtl
Running optimization stage 1 on frame_filters .......
@W:CL168 : frame_filters.vhd(367) | Removing instance range_filter_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : frame_filters.vhd(352) | Removing instance bit_filter_C_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : frame_filters.vhd(338) | Removing instance bit_filter_B_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : frame_filters.vhd(324) | Removing instance bit_filter_A_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
Finished optimization stage 1 on frame_filters (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : tx_arbitrator.vhd(100) | Synthesizing ctu_can_fd_rtl.tx_arbitrator.rtl.
@N:CD630 : tx_arbitrator_fsm.vhd(98) | Synthesizing ctu_can_fd_rtl.tx_arbitrator_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(173) | Using onehot encoding for type t_tx_arb_state. For example, enumeration s_arb_idle is mapped to "10000000".
Post processing for ctu_can_fd_rtl.tx_arbitrator_fsm.rtl
Running optimization stage 1 on tx_arbitrator_fsm .......
Finished optimization stage 1 on tx_arbitrator_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : priority_decoder.vhd(96) | Synthesizing ctu_can_fd_rtl.priority_decoder.rtl.
@N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(233) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(278) | OTHERS clause is not synthesized.
@N:CD604 : priority_decoder.vhd(278) | OTHERS clause is not synthesized.
Post processing for ctu_can_fd_rtl.priority_decoder.rtl
Running optimization stage 1 on priority_decoder .......
Finished optimization stage 1 on priority_decoder (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.tx_arbitrator.rtl
Running optimization stage 1 on tx_arbitrator .......
Finished optimization stage 1 on tx_arbitrator (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
@N:CD630 : inf_ram_wrapper.vhd(85) | Synthesizing ctu_can_fd_rtl.inf_ram_wrapper.rtl.
Post processing for ctu_can_fd_rtl.inf_ram_wrapper.rtl
Running optimization stage 1 on inf_ram_wrapper .......
@N:CL134 : inf_ram_wrapper.vhd(203) | Found RAM ram_memory, depth=21, width=8
@N:CL134 : inf_ram_wrapper.vhd(203) | Found RAM ram_memory, depth=21, width=8
@N:CL134 : inf_ram_wrapper.vhd(203) | Found RAM ram_memory, depth=21, width=8
@N:CL134 : inf_ram_wrapper.vhd(203) | Found RAM ram_memory, depth=21, width=8
Finished optimization stage 1 on inf_ram_wrapper (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : clk_gate.vhd(83) | Synthesizing ctu_can_fd_rtl.clk_gate.rtl.
Post processing for ctu_can_fd_rtl.clk_gate.rtl
Running optimization stage 1 on clk_gate .......
Finished optimization stage 1 on clk_gate (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : txt_buffer.vhd(96) | Synthesizing ctu_can_fd_rtl.txt_buffer.rtl.
@N:CD630 : txt_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.txt_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(185) | Using onehot encoding for type t_txt_buf_state. For example, enumeration s_txt_empty is mapped to "10000000".
Post processing for ctu_can_fd_rtl.txt_buffer_fsm.rtl
Running optimization stage 1 on txt_buffer_fsm .......
Finished optimization stage 1 on txt_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : txt_buffer_ram.vhd(104) | Synthesizing ctu_can_fd_rtl.txt_buffer_ram.rtl.
Post processing for ctu_can_fd_rtl.txt_buffer_ram.rtl
Running optimization stage 1 on txt_buffer_ram .......
Finished optimization stage 1 on txt_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
Post processing for ctu_can_fd_rtl.txt_buffer.rtl
Running optimization stage 1 on txt_buffer .......
Finished optimization stage 1 on txt_buffer (CPU Time 0h:00m:00s, Memory Used current: 165MB peak: 165MB)
@N:CD630 : rx_buffer.vhd(99) | Synthesizing ctu_can_fd_rtl.rx_buffer.rtl.
@N:CD364 : rx_buffer.vhd(793) | Removing redundant assignment.
@N:CD364 : rx_buffer.vhd(824) | Removing redundant assignment.
@N:CD630 : rx_buffer_ram.vhd(105) | Synthesizing ctu_can_fd_rtl.rx_buffer_ram.rtl.
@N:CD630 : inf_ram_wrapper.vhd(85) | Synthesizing ctu_can_fd_rtl.inf_ram_wrapper.rtl.
Post processing for ctu_can_fd_rtl.inf_ram_wrapper.rtl
Running optimization stage 1 on inf_ram_wrapper .......
@N:CL134 : inf_ram_wrapper.vhd(203) | Found RAM ram_memory, depth=32, width=8
@N:CL134 : inf_ram_wrapper.vhd(203) | Found RAM ram_memory, depth=32, width=8
@N:CL134 : inf_ram_wrapper.vhd(203) | Found RAM ram_memory, depth=32, width=8
@N:CL134 : inf_ram_wrapper.vhd(203) | Found RAM ram_memory, depth=32, width=8
Finished optimization stage 1 on inf_ram_wrapper (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 166MB)
Post processing for ctu_can_fd_rtl.rx_buffer_ram.rtl
Running optimization stage 1 on rx_buffer_ram .......
Finished optimization stage 1 on rx_buffer_ram (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 166MB)
@N:CD630 : rx_buffer_pointers.vhd(101) | Synthesizing ctu_can_fd_rtl.rx_buffer_pointers.rtl.
Post processing for ctu_can_fd_rtl.rx_buffer_pointers.rtl
Running optimization stage 1 on rx_buffer_pointers .......
Finished optimization stage 1 on rx_buffer_pointers (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 166MB)
@N:CD630 : rx_buffer_fsm.vhd(94) | Synthesizing ctu_can_fd_rtl.rx_buffer_fsm.rtl.
@N:CD231 : can_types_pkg.vhd(161) | Using onehot encoding for type t_rx_buf_state. For example, enumeration s_rxb_idle is mapped to "10000000".
Post processing for ctu_can_fd_rtl.rx_buffer_fsm.rtl
Running optimization stage 1 on rx_buffer_fsm .......
Finished optimization stage 1 on rx_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 166MB)
Post processing for ctu_can_fd_rtl.rx_buffer.rtl
Running optimization stage 1 on rx_buffer .......
Finished optimization stage 1 on rx_buffer (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 166MB)
@N:CD630 : memory_registers.vhd(97) | Synthesizing ctu_can_fd_rtl.memory_registers.rtl.
@N:CD630 : test_registers_reg_map.vhd(81) | Synthesizing ctu_can_fd_rtl.test_registers_reg_map.rtl.
@N:CD630 : data_mux.vhd(74) | Synthesizing ctu_can_fd_rtl.data_mux.rtl.
Post processing for ctu_can_fd_rtl.data_mux.rtl
Running optimization stage 1 on data_mux .......
Finished optimization stage 1 on data_mux (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 171MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 171MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 171MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 171MB)
@N:CD630 : address_decoder.vhd(41) | Synthesizing ctu_can_fd_rtl.address_decoder.rtl.
Post processing for ctu_can_fd_rtl.address_decoder.rtl
Running optimization stage 1 on address_decoder .......
Finished optimization stage 1 on address_decoder (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 171MB)
Post processing for ctu_can_fd_rtl.test_registers_reg_map.rtl
Running optimization stage 1 on test_registers_reg_map .......
Finished optimization stage 1 on test_registers_reg_map (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 171MB)
@N:CD630 : control_registers_reg_map.vhd(81) | Synthesizing ctu_can_fd_rtl.control_registers_reg_map.rtl.
@N:CD630 : data_mux.vhd(74) | Synthesizing ctu_can_fd_rtl.data_mux.rtl.
Post processing for ctu_can_fd_rtl.data_mux.rtl
Running optimization stage 1 on data_mux .......
Finished optimization stage 1 on data_mux (CPU Time 0h:00m:06s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : access_signaler.vhd(40) | Synthesizing ctu_can_fd_rtl.access_signaller.rtl.
Post processing for ctu_can_fd_rtl.access_signaller.rtl
Running optimization stage 1 on access_signaller .......
Finished optimization stage 1 on access_signaller (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
@N:CD630 : memory_reg.vhd(41) | Synthesizing ctu_can_fd_rtl.memory_reg.rtl.
Post processing for ctu_can_fd_rtl.memory_reg.rtl
Running optimization stage 1 on memory_reg .......
Finished optimization stage 1 on memory_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)

Only the first 100 messages of id 'CD630' are reported. To see all messages use 'report_messages -log /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/synlog/can_top_level_compiler.srr -id CD630' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CD630} -count unlimited' in the Tcl shell.
Post processing for ctu_can_fd_rtl.address_decoder.rtl
Running optimization stage 1 on address_decoder .......
Finished optimization stage 1 on address_decoder (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Post processing for ctu_can_fd_rtl.control_registers_reg_map.rtl
Running optimization stage 1 on control_registers_reg_map .......
Finished optimization stage 1 on control_registers_reg_map (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Post processing for ctu_can_fd_rtl.memory_registers.rtl
Running optimization stage 1 on memory_registers .......
Finished optimization stage 1 on memory_registers (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Post processing for ctu_can_fd_rtl.rst_sync.rtl
Running optimization stage 1 on rst_sync .......
Finished optimization stage 1 on rst_sync (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Post processing for ctu_can_fd_rtl.can_top_level.rtl
Running optimization stage 1 on can_top_level .......
Finished optimization stage 1 on can_top_level (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on rst_sync_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on rst_sync_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on address_decoder_ctu_can_fd_rtl_can_top_level_rtl_1layer0 .......
@N:CL159 : address_decoder.vhd(64) | Input clk_sys is unused.
@N:CL159 : address_decoder.vhd(65) | Input res_n is unused.
Finished optimization stage 2 on address_decoder_ctu_can_fd_rtl_can_top_level_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_3layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_3layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_4layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_4layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_5layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 11 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : memory_reg.vhd(76) | Input port bit 0 of data_in(31 downto 0) is unused 
@W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 2 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(70) | Input clk_sys is unused.
@N:CL159 : memory_reg.vhd(71) | Input res_n is unused.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_5layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_6layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 12 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(70) | Input clk_sys is unused.
@N:CL159 : memory_reg.vhd(71) | Input res_n is unused.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_6layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_7layer0 .......
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_7layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_8layer0 .......
@W:CL247 : memory_reg.vhd(76) | Input port bit 18 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 12 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 6 of data_in(31 downto 0) is unused 
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_8layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_9layer0 .......
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_9layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_10layer0 .......
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_10layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_11layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 13 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 2 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_11layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_12layer0 .......
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_12layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_13layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 7 to 1 of data_in(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_13layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on access_signaller_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@N:CL159 : access_signaler.vhd(65) | Input clk_sys is unused.
@N:CL159 : access_signaler.vhd(66) | Input res_n is unused.
@N:CL159 : access_signaler.vhd(77) | Input write is unused.
Finished optimization stage 2 on access_signaller_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_14layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 7 to 3 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_14layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_15layer0 .......
@W:CL247 : memory_reg.vhd(76) | Input port bit 31 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 27 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 23 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 19 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 15 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 11 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 7 of data_in(31 downto 0) is unused 
@W:CL247 : memory_reg.vhd(76) | Input port bit 3 of data_in(31 downto 0) is unused 
@N:CL159 : memory_reg.vhd(84) | Input lock is unused.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_15layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_16layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 15 to 10 of data_in(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_16layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on data_mux_ctu_can_fd_rtl_can_top_level_rtl_1layer0 .......
Finished optimization stage 2 on data_mux_ctu_can_fd_rtl_can_top_level_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on control_registers_reg_map_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@W:CL246 : control_registers_reg_map.vhd(97) | Input port bits 15 to 8 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : control_registers_reg_map.vhd(97) | Input port bits 1 to 0 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on control_registers_reg_map_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on address_decoder_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@N:CL159 : address_decoder.vhd(64) | Input clk_sys is unused.
@N:CL159 : address_decoder.vhd(65) | Input res_n is unused.
Finished optimization stage 2 on address_decoder_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 2 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_reg.vhd(79) | Input port bits 3 to 1 of w_be(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_1layer0 .......
@W:CL246 : memory_reg.vhd(76) | Input port bits 31 to 20 of data_in(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : memory_reg.vhd(79) | Input port bit 3 of w_be(3 downto 0) is unused 
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_2layer0 .......
Finished optimization stage 2 on memory_reg_ctu_can_fd_rtl_can_top_level_rtl_2layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on data_mux_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on data_mux_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on test_registers_reg_map_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@W:CL246 : test_registers_reg_map.vhd(92) | Input port bits 15 to 8 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : test_registers_reg_map.vhd(92) | Input port bits 1 to 0 of address(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : test_registers_reg_map.vhd(100) | Input lock_2 is unused.
Finished optimization stage 2 on test_registers_reg_map_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on memory_registers_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@W:CL246 : memory_registers.vhd(196) | Input port bits 511 to 386 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : memory_registers.vhd(196) | Input port bit 383 of stat_bus(511 downto 0) is unused 
@W:CL246 : memory_registers.vhd(196) | Input port bits 369 to 306 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 299 to 297 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 256 to 252 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 187 to 110 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 98 to 90 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : memory_registers.vhd(196) | Input port bit 80 of stat_bus(511 downto 0) is unused 
@W:CL246 : memory_registers.vhd(196) | Input port bits 70 to 10 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : memory_registers.vhd(196) | Input port bits 8 to 6 of stat_bus(511 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on memory_registers_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on rx_buffer_fsm .......
@N:CL201 : rx_buffer_fsm.vhd(311) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on rx_buffer_fsm (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on rx_buffer_pointers_32 .......
Finished optimization stage 2 on rx_buffer_pointers_32 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on inf_ram_wrapper_32_32_12_true_false .......
@W:CL246 : inf_ram_wrapper.vhd(114) | Input port bits 11 to 5 of addr_a(11 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : inf_ram_wrapper.vhd(129) | Input port bits 11 to 5 of addr_b(11 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : inf_ram_wrapper.vhd(108) | Input res_n is unused.
Finished optimization stage 2 on inf_ram_wrapper_32_32_12_true_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on rx_buffer_ram_32_false_false .......
@W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 47 to 44 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : rx_buffer_ram.vhd(130) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on rx_buffer_ram_32_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on rx_buffer_32_false_false_1 .......
@W:CL246 : rx_buffer.vhd(224) | Input port bits 1023 to 477 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : rx_buffer.vhd(224) | Input port bits 475 to 355 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : rx_buffer.vhd(224) | Input port bits 349 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on rx_buffer_32_false_false_1 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_ram_0_false_false .......
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_0_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_fsm_0 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_4_0_1_false_false .......
@W:CL246 : txt_buffer.vhd(147) | Input port bits 3 to 1 of txtb_sw_cmd_index(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : txt_buffer.vhd(162) | Input drv_txbbm_ena is unused.
Finished optimization stage 2 on txt_buffer_4_0_1_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_ram_1_false_false .......
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_1_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_fsm_1 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_1 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_4_1_1_false_false .......
@W:CL246 : txt_buffer.vhd(147) | Input port bits 3 to 2 of txtb_sw_cmd_index(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL247 : txt_buffer.vhd(147) | Input port bit 0 of txtb_sw_cmd_index(3 downto 0) is unused 
Finished optimization stage 2 on txt_buffer_4_1_1_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_ram_2_false_false .......
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_2_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_fsm_2 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_2 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_4_2_1_false_false .......
@W:CL247 : txt_buffer.vhd(147) | Input port bit 3 of txtb_sw_cmd_index(3 downto 0) is unused 
@W:CL246 : txt_buffer.vhd(147) | Input port bits 1 to 0 of txtb_sw_cmd_index(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : txt_buffer.vhd(162) | Input drv_txbbm_ena is unused.
Finished optimization stage 2 on txt_buffer_4_2_1_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on clk_gate_1 .......
@N:CL159 : clk_gate.vhd(92) | Input clk_en is unused.
@N:CL159 : clk_gate.vhd(95) | Input scan_enable is unused.
Finished optimization stage 2 on clk_gate_1 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on inf_ram_wrapper_32_21_5_true_false .......
@N:CL159 : inf_ram_wrapper.vhd(108) | Input res_n is unused.
Finished optimization stage 2 on inf_ram_wrapper_32_21_5_true_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_ram_3_false_false .......
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 63 to 52 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 47 to 37 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : txt_buffer_ram.vhd(129) | Input port bits 31 to 2 of test_registers_out(95 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_ram_3_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_fsm_3 .......
@N:CL201 : txt_buffer_fsm.vhd(402) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Finished optimization stage 2 on txt_buffer_fsm_3 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on txt_buffer_4_3_1_false_false .......
@W:CL246 : txt_buffer.vhd(147) | Input port bits 2 to 0 of txtb_sw_cmd_index(3 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on txt_buffer_4_3_1_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on priority_decoder_4 .......
Finished optimization stage 2 on priority_decoder_4 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on tx_arbitrator_fsm .......
@N:CL201 : tx_arbitrator_fsm.vhd(524) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@W:CL246 : tx_arbitrator_fsm.vhd(128) | Input port bits 5 to 2 of txtb_hw_cmd(5 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on tx_arbitrator_fsm (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on tx_arbitrator_4 .......
@W:CL247 : tx_arbitrator.vhd(125) | Input port bit 3 of txtb_allow_bb(3 downto 0) is unused 
@W:CL247 : tx_arbitrator.vhd(125) | Input port bit 1 of txtb_allow_bb(3 downto 0) is unused 
@W:CL246 : tx_arbitrator.vhd(200) | Input port bits 1023 to 477 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : tx_arbitrator.vhd(200) | Input port bits 474 to 473 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : tx_arbitrator.vhd(200) | Input port bits 471 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on tx_arbitrator_4 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bit_filter_29_false .......
@N:CL159 : bit_filter.vhd(102) | Input filter_mask is unused.
@N:CL159 : bit_filter.vhd(105) | Input filter_value is unused.
@N:CL159 : bit_filter.vhd(108) | Input filter_input is unused.
@N:CL159 : bit_filter.vhd(111) | Input enable is unused.
Finished optimization stage 2 on bit_filter_29_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on range_filter_29_false .......
@N:CL159 : range_filter.vhd(104) | Input filter_upp_th is unused.
@N:CL159 : range_filter.vhd(107) | Input filter_low_th is unused.
@N:CL159 : range_filter.vhd(110) | Input filter_input is unused.
@N:CL159 : range_filter.vhd(113) | Input enable is unused.
Finished optimization stage 2 on range_filter_29_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on frame_filters_false_false_false_false .......
@N:CL159 : frame_filters.vhd(129) | Input drv_bus is unused.
@N:CL159 : frame_filters.vhd(135) | Input rec_ident is unused.
@N:CL159 : frame_filters.vhd(138) | Input rec_ident_type is unused.
@N:CL159 : frame_filters.vhd(141) | Input rec_frame_type is unused.
@N:CL159 : frame_filters.vhd(144) | Input rec_is_rtr is unused.
Finished optimization stage 2 on frame_filters_false_false_false_false (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on int_module .......
Finished optimization stage 2 on int_module (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on int_manager_12_4 .......
@W:CL246 : int_manager.vhd(157) | Input port bits 1023 to 876 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 863 to 844 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 831 to 812 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 799 to 780 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 767 to 748 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : int_manager.vhd(157) | Input port bits 735 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on int_manager_12_4 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on endian_swapper_true_4_8 .......
Finished optimization stage 2 on endian_swapper_true_4_8 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on dlc_decoder .......
Finished optimization stage 2 on dlc_decoder (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on protocol_control_fsm .......
@N:CL201 : protocol_control_fsm.vhd(2988) | Trying to extract state machine for register sp_control_q_i.
Extracted state machine for register sp_control_q_i
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : protocol_control_fsm.vhd(2840) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 38 reachable states with original encodings of:
   00000000000000000000000000000000000001
   00000000000000000000000000000000000010
   00000000000000000000000000000000000100
   00000000000000000000000000000000001000
   00000000000000000000000000000000010000
   00000000000000000000000000000000100000
   00000000000000000000000000000001000000
   00000000000000000000000000000010000000
   00000000000000000000000000000100000000
   00000000000000000000000000001000000000
   00000000000000000000000000010000000000
   00000000000000000000000000100000000000
   00000000000000000000000001000000000000
   00000000000000000000000010000000000000
   00000000000000000000000100000000000000
   00000000000000000000001000000000000000
   00000000000000000000010000000000000000
   00000000000000000000100000000000000000
   00000000000000000001000000000000000000
   00000000000000000010000000000000000000
   00000000000000000100000000000000000000
   00000000000000001000000000000000000000
   00000000000000010000000000000000000000
   00000000000000100000000000000000000000
   00000000000001000000000000000000000000
   00000000000010000000000000000000000000
   00000000000100000000000000000000000000
   00000000001000000000000000000000000000
   00000000010000000000000000000000000000
   00000000100000000000000000000000000000
   00000001000000000000000000000000000000
   00000010000000000000000000000000000000
   00000100000000000000000000000000000000
   00001000000000000000000000000000000000
   00010000000000000000000000000000000000
   00100000000000000000000000000000000000
   01000000000000000000000000000000000000
   10000000000000000000000000000000000000
Finished optimization stage 2 on protocol_control_fsm (CPU Time 0h:00m:01s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on control_counter_9 .......
Finished optimization stage 2 on control_counter_9 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on reintegration_counter .......
Finished optimization stage 2 on reintegration_counter (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on retransmitt_counter_4 .......
Finished optimization stage 2 on retransmitt_counter_4 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on err_detector_true .......
Finished optimization stage 2 on err_detector_true (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on shift_reg_preload_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on shift_reg_preload_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on tx_shift_reg .......
Finished optimization stage 2 on tx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on shift_reg_byte_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@W:CL247 : shift_reg_byte.vhd(117) | Input port bit 0 of byte_input_sel(3 downto 0) is unused 
Finished optimization stage 2 on shift_reg_byte_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on rx_shift_reg .......
Finished optimization stage 2 on rx_shift_reg (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on protocol_control_9_4_true .......
@W:CL246 : protocol_control.vhd(128) | Input port bits 1023 to 514 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 506 to 478 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 476 to 472 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 464 to 461 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 459 to 430 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 428 to 375 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : protocol_control.vhd(128) | Input port bits 372 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on protocol_control_9_4_true (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on operation_control .......
@N:CL201 : operation_control.vhd(227) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on operation_control (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on fault_confinement_fsm .......
@N:CL201 : fault_confinement_fsm.vhd(274) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Finished optimization stage 2 on fault_confinement_fsm (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on err_counters .......
Finished optimization stage 2 on err_counters (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on fault_confinement_rules .......
@N:CL159 : fault_confinement_rules.vhd(100) | Input clk_sys is unused.
Finished optimization stage 2 on fault_confinement_rules (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on fault_confinement .......
@W:CL246 : fault_confinement.vhd(114) | Input port bits 1023 to 514 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : fault_confinement.vhd(114) | Input port bits 512 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : fault_confinement.vhd(114) | Input port bits 508 to 427 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : fault_confinement.vhd(114) | Input port bits 399 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : fault_confinement.vhd(163) | Input rec_valid is unused.
Finished optimization stage 2 on fault_confinement (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_can_top_level_rtl_1layer0 .......
Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_can_top_level_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on crc_calc_ctu_can_fd_rtl_can_top_level_rtl_2layer0 .......
Finished optimization stage 2 on crc_calc_ctu_can_fd_rtl_can_top_level_rtl_2layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on can_crc_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@W:CL246 : can_crc.vhd(129) | Input port bits 1023 to 511 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : can_crc.vhd(129) | Input port bits 509 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on can_crc_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bit_stuffing .......
Finished optimization stage 2 on bit_stuffing (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on dff_arst_ctu_can_fd_rtl_can_top_level_rtl_1layer0 .......
Finished optimization stage 2 on dff_arst_ctu_can_fd_rtl_can_top_level_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_can_top_level_rtl_1layer0 .......
Finished optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_can_top_level_rtl_1layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bit_destuffing .......
Finished optimization stage 2 on bit_destuffing (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bus_traffic_counters .......
Finished optimization stage 2 on bus_traffic_counters (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on dff_arst_ce_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on trigger_mux_2 .......
Finished optimization stage 2 on trigger_mux_2 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on can_core_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on can_core_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bit_time_cfg_capture_8_8_8_5_8_8_8_5 .......
@W:CL246 : bit_time_cfg_capture.vhd(136) | Input port bits 1023 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : bit_time_cfg_capture.vhd(136) | Input port bits 508 to 61 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on bit_time_cfg_capture_8_8_8_5_8_8_8_5 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on synchronisation_checker .......
Finished optimization stage 2 on synchronisation_checker (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bit_segment_meter_5_8_8_9 .......
Finished optimization stage 2 on bit_segment_meter_5_8_8_9 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bit_time_counters_9_8 .......
Finished optimization stage 2 on bit_time_counters_9_8 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on segment_end_detector .......
Finished optimization stage 2 on segment_end_detector (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bit_time_fsm .......
@N:CL201 : bit_time_fsm.vhd(208) | Trying to extract state machine for register current_state.
Extracted state machine for register current_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Finished optimization stage 2 on bit_time_fsm (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on trigger_generator_2 .......
Finished optimization stage 2 on trigger_generator_2 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on prescaler_8_8_8_5_8_8_8_5_2 .......
Finished optimization stage 2 on prescaler_8_8_8_5_8_8_8_5_2 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on sig_sync_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on sig_sync_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on trv_delay_measurement_7_8_true_255 .......
Finished optimization stage 2 on trv_delay_measurement_7_8_true_255 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on data_edge_detector .......
Finished optimization stage 2 on data_edge_detector (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on mux2 .......
Finished optimization stage 2 on mux2 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on rst_reg_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on rst_reg_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on dff_arst_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
Finished optimization stage 2 on dff_arst_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on ssp_generator_15 .......
Finished optimization stage 2 on ssp_generator_15 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on tx_data_cache_ctu_can_fd_rtl_can_top_level_rtl_0layer0 .......
@N:CL134 : tx_data_cache.vhd(189) | Found RAM tx_cache, depth=8, width=1
Finished optimization stage 2 on tx_data_cache_ctu_can_fd_rtl_can_top_level_rtl_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bit_err_detector .......
Finished optimization stage 2 on bit_err_detector (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on sample_mux .......
Finished optimization stage 2 on sample_mux (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on bus_sampling_255_8_7_8_true_15 .......
@W:CL246 : bus_sampling.vhd(145) | Input port bits 1023 to 510 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : bus_sampling.vhd(145) | Input port bits 508 to 383 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : bus_sampling.vhd(145) | Input port bits 372 to 0 of drv_bus(1023 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on bus_sampling_255_8_7_8_true_15 (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)
Running optimization stage 2 on can_top_level .......
Finished optimization stage 2 on can_top_level (CPU Time 0h:00m:00s, Memory Used current: 370MB peak: 370MB)

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_vhdl Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 370MB peak: 370MB)


Process completed successfully.
# Fri Jul 15 21:02:23 2022

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63093
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Jul 15 21:02:24 2022

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  can_top_level_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 43MB peak: 43MB)

Process took 0h:00m:15s realtime, 0h:00m:14s cputime

Process completed successfully.
# Fri Jul 15 21:02:24 2022

###########################################################]


###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63093
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202109synp1, Build 219R, Built Feb 23 2022 09:48:52, @4155246

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 153MB peak: 154MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Jul 15 21:02:26 2022

###########################################################]


Premap Report



# Fri Jul 15 21:02:27 2022


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63093
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Generic Technology Pre-mapping, Version map202109act, Build 055R, Built Feb 23 2022 09:46:51, @4155246


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 221MB peak: 221MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 238MB)

Reading constraint file: /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/designer/can_top_level/synthesis.fdc
Linked File:  can_top_level_scck.rpt
See clock summary report "/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/can_top_level_scck.rpt"
@N:MF472 :  | Synthesis running in Automatic Compile Point mode 
@N:MF474 :  | No compile point is identified in Automatic Compile Point mode 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 263MB peak: 263MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 263MB peak: 263MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 263MB peak: 263MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 265MB peak: 265MB)


#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####

Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 296MB peak: 296MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 296MB peak: 296MB)

@N:BN115 : memory_registers.vhd(505) | Removing instance clk_gate_control_regs_comp (in view: ctu_can_fd_rtl.memory_registers_ctu_can_fd_rtl_can_top_level_rtl_0layer0(rtl)) because it does not drive other instances.
@N:BN115 : memory_registers.vhd(517) | Removing instance clk_gate_test_regs_comp (in view: ctu_can_fd_rtl.memory_registers_ctu_can_fd_rtl_can_top_level_rtl_0layer0(rtl)) because it does not drive other instances.
@N:BN115 : rx_buffer.vhd(841) | Removing instance clk_gate_rx_buffer_ram_comp (in view: ctu_can_fd_rtl.rx_buffer_32_false_false_1(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(345) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_4_3_1_false_false(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(345) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_4_2_1_false_false(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(345) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_4_0_1_false_false(rtl)) because it does not drive other instances.
@N:BN115 : txt_buffer.vhd(345) | Removing instance clk_gate_txt_buffer_ram_comp (in view: ctu_can_fd_rtl.txt_buffer_4_1_1_false_false(rtl)) because it does not drive other instances.
@N:BN115 : protocol_control.vhd(689) | Removing instance endian_swapper_tx_inst (in view: ctu_can_fd_rtl.protocol_control_9_4_true(rtl)) because it does not drive other instances.
@N:BN362 : memory_reg.vhd(170) | Removing sequential instance reg_value_r[12] (in view: ctu_can_fd_rtl.memory_reg_ctu_can_fd_rtl_can_top_level_rtl_14layer0(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : memory_reg.vhd(170) | Removing sequential instance reg_value_r[13] (in view: ctu_can_fd_rtl.memory_reg_ctu_can_fd_rtl_can_top_level_rtl_14layer0(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : memory_reg.vhd(170) | Removing sequential instance reg_value_r[14] (in view: ctu_can_fd_rtl.memory_reg_ctu_can_fd_rtl_can_top_level_rtl_14layer0(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : memory_reg.vhd(170) | Removing sequential instance reg_value_r[15] (in view: ctu_can_fd_rtl.memory_reg_ctu_can_fd_rtl_can_top_level_rtl_14layer0(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tx_arbitrator.vhd(557) | Removing sequential instance txtb_clk_en_q (in view: ctu_can_fd_rtl.tx_arbitrator_4(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : protocol_control_fsm.vhd(3231) | Removing sequential instance txtb_clk_en_q (in view: ctu_can_fd_rtl.protocol_control_fsm(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:FP130 :  | Promoting Net clk_sys on CLKINT  I_1  
@N:FX1184 :  | Applying syn_allowed_resources blockrams=952 on top level netlist can_top_level  

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 298MB peak: 298MB)



Clock Summary
******************

          Start                     Requested     Requested     Clock        Clock          Clock
Level     Clock                     Frequency     Period        Type         Group          Load 
-------------------------------------------------------------------------------------------------
0 -       can_top_level|clk_sys     100.0 MHz     10.000        inferred     (multiple)     1501 
=================================================================================================



Clock Load Summary
***********************

                          Clock     Source            Clock Pin                                             Non-clock Pin     Non-clock Pin
Clock                     Load      Pin               Seq Example                                           Seq Example       Comb Example 
-------------------------------------------------------------------------------------------------------------------------------------------
can_top_level|clk_sys     1501      clk_sys(port)     bus_sampling_inst.sample_mux_inst.prev_sample_q.C     -                 I_1.A(CLKINT)
===========================================================================================================================================

@W:MT530 : rst_sync.vhd(104) | Found inferred clock can_top_level|clk_sys which controls 1501 sequential elements including rst_sync_inst.rff. This clock has no specified timing constraint which may adversely impact design performance. 

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/can_top_level.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 298MB peak: 298MB)

Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.rx_buffer_fsm(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_3(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_2(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_0(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_1(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.tx_arbitrator_fsm(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine sp_control_q_i[0:2] (in view: ctu_can_fd_rtl.protocol_control_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine curr_state[0:37] (in view: ctu_can_fd_rtl.protocol_control_fsm(rtl))
original code -> new code
   00000000000000000000000000000000000001 -> 00000000000000000000000000000000000001
   00000000000000000000000000000000000010 -> 00000000000000000000000000000000000010
   00000000000000000000000000000000000100 -> 00000000000000000000000000000000000100
   00000000000000000000000000000000001000 -> 00000000000000000000000000000000001000
   00000000000000000000000000000000010000 -> 00000000000000000000000000000000010000
   00000000000000000000000000000000100000 -> 00000000000000000000000000000000100000
   00000000000000000000000000000001000000 -> 00000000000000000000000000000001000000
   00000000000000000000000000000010000000 -> 00000000000000000000000000000010000000
   00000000000000000000000000000100000000 -> 00000000000000000000000000000100000000
   00000000000000000000000000001000000000 -> 00000000000000000000000000001000000000
   00000000000000000000000000010000000000 -> 00000000000000000000000000010000000000
   00000000000000000000000000100000000000 -> 00000000000000000000000000100000000000
   00000000000000000000000001000000000000 -> 00000000000000000000000001000000000000
   00000000000000000000000010000000000000 -> 00000000000000000000000010000000000000
   00000000000000000000000100000000000000 -> 00000000000000000000000100000000000000
   00000000000000000000001000000000000000 -> 00000000000000000000001000000000000000
   00000000000000000000010000000000000000 -> 00000000000000000000010000000000000000
   00000000000000000000100000000000000000 -> 00000000000000000000100000000000000000
   00000000000000000001000000000000000000 -> 00000000000000000001000000000000000000
   00000000000000000010000000000000000000 -> 00000000000000000010000000000000000000
   00000000000000000100000000000000000000 -> 00000000000000000100000000000000000000
   00000000000000001000000000000000000000 -> 00000000000000001000000000000000000000
   00000000000000010000000000000000000000 -> 00000000000000010000000000000000000000
   00000000000000100000000000000000000000 -> 00000000000000100000000000000000000000
   00000000000001000000000000000000000000 -> 00000000000001000000000000000000000000
   00000000000010000000000000000000000000 -> 00000000000010000000000000000000000000
   00000000000100000000000000000000000000 -> 00000000000100000000000000000000000000
   00000000001000000000000000000000000000 -> 00000000001000000000000000000000000000
   00000000010000000000000000000000000000 -> 00000000010000000000000000000000000000
   00000000100000000000000000000000000000 -> 00000000100000000000000000000000000000
   00000001000000000000000000000000000000 -> 00000001000000000000000000000000000000
   00000010000000000000000000000000000000 -> 00000010000000000000000000000000000000
   00000100000000000000000000000000000000 -> 00000100000000000000000000000000000000
   00001000000000000000000000000000000000 -> 00001000000000000000000000000000000000
   00010000000000000000000000000000000000 -> 00010000000000000000000000000000000000
   00100000000000000000000000000000000000 -> 00100000000000000000000000000000000000
   01000000000000000000000000000000000000 -> 01000000000000000000000000000000000000
   10000000000000000000000000000000000000 -> 10000000000000000000000000000000000000
Encoding state machine curr_state[0:3] (in view: ctu_can_fd_rtl.operation_control(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : operation_control.vhd(227) | There are no possible illegal states for state machine curr_state[0:3] (in view: ctu_can_fd_rtl.operation_control(rtl)); safe FSM implementation is not required.
Encoding state machine curr_state[0:2] (in view: ctu_can_fd_rtl.fault_confinement_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine current_state[0:2] (in view: ctu_can_fd_rtl.bit_time_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 323MB peak: 323MB)


Finished constraint checker (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 325MB peak: 325MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 325MB peak: 325MB)

Process took 0h:00m:06s realtime, 0h:00m:05s cputime
# Fri Jul 15 21:02:33 2022

###########################################################]


Map & Optimize Report



# Fri Jul 15 21:02:34 2022


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M
Install: /opt/microsemi/Libero_SoC_v2022.1/SynplifyPro
OS: Ubuntu 20.04.4 LTS
Hostname: ondrej-Aspire-V3-771
max virtual memory: unlimited (bytes)
max user processes: 63093
max stack size: 8388608 (bytes)


Implementation : synthesis
Synopsys Generic Technology Mapper, Version map202109act, Build 055R, Built Feb 23 2022 09:46:51, @4155246


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 221MB peak: 221MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 233MB peak: 233MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 233MB peak: 233MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 233MB peak: 233MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 233MB peak: 233MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 279MB peak: 279MB)


Available hyper_sources - for debug and ip models
	None Found


#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####
@W:FA239 : rx_buffer.vhd(628) | ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W:FA239 : rx_buffer.vhd(628) | ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N:MO106 : rx_buffer.vhd(628) | Found ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 16 words by 5 bits.

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 286MB peak: 286MB)

@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM rx_buffer_inst.rx_buffer_ram_inst.rx_buf_RAM_inst.ram_memory_3[31:0] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM rx_buffer_inst.rx_buffer_ram_inst.rx_buf_RAM_inst.ram_memory_3[31:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX702 : inf_ram_wrapper.vhd(143) | Found startup values on RAM instance rx_buffer_inst.rx_buffer_ram_inst.rx_buf_RAM_inst.ram_memory_3[31:0] (in view: ctu_can_fd_rtl.can_top_level(rtl)).
@N:FX702 : inf_ram_wrapper.vhd(143) | Found startup values on RAM instance rx_buffer_inst.rx_buffer_ram_inst.rx_buf_RAM_inst.ram_memory_3[31:0]
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.1\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.0\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.2\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_3[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_2[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory_1[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : inf_ram_wrapper.vhd(143) | Property "block_ram" or "no_rw_check" found for RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] with specified coding style. Inferring block RAM.
@W:FX107 : inf_ram_wrapper.vhd(143) | RAM txt_buf_comp_gen\.3\.txt_buffer_inst.txt_buffer_ram_inst.txt_buf_ram_inst.ram_memory[0:7] (in view: ctu_can_fd_rtl.can_top_level(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:MO160 : memory_registers.vhd(763) | Register bit memory_registers_inst.tx_double_parity_error (in view view:ctu_can_fd_rtl.can_top_level(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : memory_registers.vhd(763) | Register bit memory_registers_inst.tx_parity_error (in view view:ctu_can_fd_rtl.can_top_level(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:MO231 : rx_buffer_pointers.vhd(285) | Found counter in view:ctu_can_fd_rtl.can_top_level(rtl) instance rx_buffer_inst.rx_buffer_pointers_inst.write_pointer_raw_i[4:0] 
@N:MO231 : rx_buffer_pointers.vhd(308) | Found counter in view:ctu_can_fd_rtl.can_top_level(rtl) instance rx_buffer_inst.rx_buffer_pointers_inst.write_pointer_ts_i[4:0] 
@N:MO231 : rx_buffer.vhd(699) | Found counter in view:ctu_can_fd_rtl.can_top_level(rtl) instance rx_buffer_inst.read_counter_q[4:0] 
@W:MO160 : tx_arbitrator.vhd(761) | Register bit tx_arbitrator_inst.txtb_pointer_meta_q[3] (in view view:ctu_can_fd_rtl.can_top_level(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:MF179 : tx_arbitrator.vhd(356) | Found 32 by 32 bit equality operator ('==') tx_arbitrator_inst.less_than\.un6_timestamp_valid (in view: ctu_can_fd_rtl.can_top_level(rtl))
@W:BN132 : tx_arbitrator.vhd(761) | Removing instance tx_arbitrator_inst.txtb_pointer_meta_q[4] because it is equivalent to instance tx_arbitrator_inst.txtb_pointer_meta_q[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.rx_buffer_fsm(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_3(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@W:MO160 : txt_buffer_fsm.vhd(402) | Register bit curr_state[0] (in view view:ctu_can_fd_rtl.txt_buffer_fsm_3(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_2(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@W:MO160 : txt_buffer_fsm.vhd(402) | Register bit curr_state[0] (in view view:ctu_can_fd_rtl.txt_buffer_fsm_2(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_0(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@W:MO160 : txt_buffer_fsm.vhd(402) | Register bit curr_state[0] (in view view:ctu_can_fd_rtl.txt_buffer_fsm_0(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.txt_buffer_fsm_1(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@W:MO160 : txt_buffer_fsm.vhd(402) | Register bit curr_state[0] (in view view:ctu_can_fd_rtl.txt_buffer_fsm_1(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine curr_state[0:7] (in view: ctu_can_fd_rtl.tx_arbitrator_fsm(rtl))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine sp_control_q_i[0:2] (in view: ctu_can_fd_rtl.protocol_control_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine curr_state[0:37] (in view: ctu_can_fd_rtl.protocol_control_fsm(rtl))
original code -> new code
   00000000000000000000000000000000000001 -> 00000000000000000000000000000000000001
   00000000000000000000000000000000000010 -> 00000000000000000000000000000000000010
   00000000000000000000000000000000000100 -> 00000000000000000000000000000000000100
   00000000000000000000000000000000001000 -> 00000000000000000000000000000000001000
   00000000000000000000000000000000010000 -> 00000000000000000000000000000000010000
   00000000000000000000000000000000100000 -> 00000000000000000000000000000000100000
   00000000000000000000000000000001000000 -> 00000000000000000000000000000001000000
   00000000000000000000000000000010000000 -> 00000000000000000000000000000010000000
   00000000000000000000000000000100000000 -> 00000000000000000000000000000100000000
   00000000000000000000000000001000000000 -> 00000000000000000000000000001000000000
   00000000000000000000000000010000000000 -> 00000000000000000000000000010000000000
   00000000000000000000000000100000000000 -> 00000000000000000000000000100000000000
   00000000000000000000000001000000000000 -> 00000000000000000000000001000000000000
   00000000000000000000000010000000000000 -> 00000000000000000000000010000000000000
   00000000000000000000000100000000000000 -> 00000000000000000000000100000000000000
   00000000000000000000001000000000000000 -> 00000000000000000000001000000000000000
   00000000000000000000010000000000000000 -> 00000000000000000000010000000000000000
   00000000000000000000100000000000000000 -> 00000000000000000000100000000000000000
   00000000000000000001000000000000000000 -> 00000000000000000001000000000000000000
   00000000000000000010000000000000000000 -> 00000000000000000010000000000000000000
   00000000000000000100000000000000000000 -> 00000000000000000100000000000000000000
   00000000000000001000000000000000000000 -> 00000000000000001000000000000000000000
   00000000000000010000000000000000000000 -> 00000000000000010000000000000000000000
   00000000000000100000000000000000000000 -> 00000000000000100000000000000000000000
   00000000000001000000000000000000000000 -> 00000000000001000000000000000000000000
   00000000000010000000000000000000000000 -> 00000000000010000000000000000000000000
   00000000000100000000000000000000000000 -> 00000000000100000000000000000000000000
   00000000001000000000000000000000000000 -> 00000000001000000000000000000000000000
   00000000010000000000000000000000000000 -> 00000000010000000000000000000000000000
   00000000100000000000000000000000000000 -> 00000000100000000000000000000000000000
   00000001000000000000000000000000000000 -> 00000001000000000000000000000000000000
   00000010000000000000000000000000000000 -> 00000010000000000000000000000000000000
   00000100000000000000000000000000000000 -> 00000100000000000000000000000000000000
   00001000000000000000000000000000000000 -> 00001000000000000000000000000000000000
   00010000000000000000000000000000000000 -> 00010000000000000000000000000000000000
   00100000000000000000000000000000000000 -> 00100000000000000000000000000000000000
   01000000000000000000000000000000000000 -> 01000000000000000000000000000000000000
   10000000000000000000000000000000000000 -> 10000000000000000000000000000000000000
@N:MO231 : control_counter.vhd(230) | Found counter in view:ctu_can_fd_rtl.control_counter_9(rtl) instance compl_ctr_q[8:0] 
@N:MO231 : control_counter.vhd(202) | Found counter in view:ctu_can_fd_rtl.control_counter_9(rtl) instance ctrl_ctr_q[8:0] 
@N:MF179 : err_detector.vhd(326) | Found 15 by 15 bit equality operator ('==') crc_15_ok (in view: ctu_can_fd_rtl.err_detector_true(rtl))
@N:MF179 : err_detector.vhd(330) | Found 17 by 17 bit equality operator ('==') crc_17_ok (in view: ctu_can_fd_rtl.err_detector_true(rtl))
@N:MF179 : err_detector.vhd(334) | Found 21 by 21 bit equality operator ('==') crc_21_ok (in view: ctu_can_fd_rtl.err_detector_true(rtl))
@N:MO231 : reintegration_counter.vhd(154) | Found counter in view:ctu_can_fd_rtl.reintegration_counter(rtl) instance reinteg_ctr_q[8:0] 
Encoding state machine curr_state[0:3] (in view: ctu_can_fd_rtl.operation_control(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : operation_control.vhd(227) | There are no possible illegal states for state machine curr_state[0:3] (in view: ctu_can_fd_rtl.operation_control(rtl)); safe FSM implementation is not required.
Encoding state machine curr_state[0:2] (in view: ctu_can_fd_rtl.fault_confinement_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@W:MO160 : bit_time_cfg_capture.vhd(284) | Register bit bit_time_cfg_capture_inst.tseg1_dbt[7] (in view view:ctu_can_fd_rtl.prescaler_8_8_8_5_8_8_8_5_2(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:MO231 : bit_time_counters.vhd(192) | Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_1(rtl) instance tq_counter_q[7:0] 
@N:MO231 : bit_time_counters.vhd(223) | Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_1(rtl) instance segm_counter_q[8:0] 
@N:MO231 : bit_time_counters.vhd(192) | Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_0(rtl) instance tq_counter_q[7:0] 
@N:MO231 : bit_time_counters.vhd(223) | Found counter in view:ctu_can_fd_rtl.bit_time_counters_9_8_0(rtl) instance segm_counter_q[8:0] 
Encoding state machine current_state[0:2] (in view: ctu_can_fd_rtl.bit_time_fsm(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:MF135 : tx_data_cache.vhd(189) | RAM tx_data_cache_inst.tx_cache (in view: ctu_can_fd_rtl.bus_sampling_255_8_7_8_true_15(rtl)) is 8 words by 1 bits.
@N:MO231 : ssp_generator.vhd(213) | Found counter in view:ctu_can_fd_rtl.ssp_generator_15(rtl) instance btmc_q[14:0] 

Starting factoring (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:05s; Memory used current: 314MB peak: 314MB)

@W:BN132 : dff_arst.vhd(106) | Removing instance can_core_inst.fault_confinement_inst.fault_confinement_fsm_inst.dff_fc_reset_inst.output because it is equivalent to instance prescaler_inst.bit_time_cfg_capture_inst.drv_ena_reg. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dff_arst.vhd(106) | Removing instance can_core_inst.trigger_mux_inst.crc_trig_tx_wbs_reg.output because it is equivalent to instance bus_sampling_inst.tx_trigger_reg_inst.output. To keep the instance, apply constraint syn_preserve=1 on the instance.

Finished factoring (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:09s; Memory used current: 342MB peak: 342MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:11s; Memory used current: 351MB peak: 351MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:12s; Memory used current: 351MB peak: 351MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:17s; Memory used current: 351MB peak: 351MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:17s; Memory used current: 351MB peak: 351MB)


Finished preparing to map (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:18s; Memory used current: 351MB peak: 351MB)


Finished technology mapping (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:20s; Memory used current: 386MB peak: 386MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:20s		    -1.34ns		3866 /      1170
   2		0h:00m:21s		    -1.34ns		3604 /      1170
   3		0h:00m:21s		    -1.33ns		3604 /      1170
@N:FX271 : trigger_generator.vhd(196) | Replicating instance prescaler_inst.trigger_generator_inst.rx_trig_req_q (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 6 loads 1 time to improve timing.
@N:FX271 : bit_time_fsm.vhd(208) | Replicating instance prescaler_inst.bit_time_fsm_inst.current_state[0] (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 35 loads 2 times to improve timing.
@N:FX271 : segment_end_detector.vhd(293) | Replicating instance prescaler_inst.segment_end_detector_inst.un1_h_sync_valid_i (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 40 loads 2 times to improve timing.
@N:FX271 : dff_arst_ce.vhd(109) | Replicating instance can_core_inst.bit_destuffing_inst.dff_data_out_val_reg.output (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 17 loads 1 time to improve timing.
Timing driven replication report
Added 4 Registers via timing driven replication
Added 4 LUTs via timing driven replication

   4		0h:00m:22s		    -0.78ns		3611 /      1174
   5		0h:00m:23s		    -0.21ns		3613 /      1174
   6		0h:00m:23s		    -0.09ns		3614 /      1174
@N:FX271 : segment_end_detector.vhd(308) | Replicating instance prescaler_inst.segment_end_detector_inst.un3_m10_0 (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 46 loads 3 times to improve timing.
@N:FX271 : memory_reg.vhd(170) | Replicating instance memory_registers_inst.control_registers_reg_map_comp.settings_reg_comp.reg_value_r[6] (in view: ctu_can_fd_rtl.can_top_level(rtl)) with 31 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 3 LUTs via timing driven replication

   7		0h:00m:23s		     0.02ns		3590 /      1175
   8		0h:00m:23s		     0.15ns		3591 /      1175
   9		0h:00m:24s		     0.17ns		3591 /      1175

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:25s; Memory used current: 386MB peak: 386MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:25s; Memory used current: 386MB peak: 386MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 1213 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

==================================== Non-Gated/Non-Generated Clocks ====================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                 
--------------------------------------------------------------------------------------------------------
ClockId0001        clk_sys             port                   1213       frame_filters_inst.ident_valid_q
========================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:26s; Memory used current: 386MB peak: 386MB)

Writing Analyst data base /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/synthesis/synwork/can_top_level_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:27s; Memory used current: 386MB peak: 386MB)

Writing Verilog Simulation files
@W:BW110 : can_top_level.vhd(103) | Renaming port can_top_level due to collision with Verilog/ System Verilog reserved word 
    int --> int_Z
@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  
@W:BW156 :  | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:28s; Memory used current: 386MB peak: 386MB)


Finished Writing Netlists (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:28s; Memory used current: 386MB peak: 386MB)


Start final timing analysis (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:29s; Memory used current: 386MB peak: 386MB)

@W:MT420 :  | Found inferred clock can_top_level|clk_sys with period 10.00ns. Please declare a user-defined clock on port clk_sys. 


##### START OF TIMING REPORT #####[
# Timing report written on Fri Jul 15 21:03:06 2022
#


Top view:               can_top_level
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    /DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/designer/can_top_level/synthesis.fdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: 1.646

                          Requested     Estimated     Requested     Estimated               Clock        Clock     
Starting Clock            Frequency     Frequency     Period        Period        Slack     Type         Group     
-------------------------------------------------------------------------------------------------------------------
can_top_level|clk_sys     100.0 MHz     119.7 MHz     10.000        8.354         1.646     inferred     (multiple)
===================================================================================================================





Clock Relationships
*******************

Clocks                                        |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------
Starting               Ending                 |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------
can_top_level|clk_sys  can_top_level|clk_sys  |  10.000      1.646  |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: can_top_level|clk_sys
====================================



Starting Points with Worst Slack
********************************

                                                                                             Starting                                                            Arrival          
Instance                                                                                     Reference                 Type     Pin     Net                      Time        Slack
                                                                                             Clock                                                                                
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
prescaler_inst.trigger_generator_inst.rx_trig_req_q_fast                                     can_top_level|clk_sys     SLE      Q       rx_trig_req_q_fast       0.218       1.646
can_core_inst.bit_destuffing_inst.dff_destuffed_flag_reg.output                              can_top_level|clk_sys     SLE      Q       destuffed                0.218       1.659
memory_registers_inst.txtb_sw_cmd\.set_abt                                                   can_top_level|clk_sys     SLE      Q       set_abt                  0.218       1.667
can_core_inst.protocol_control_inst.err_detector_inst.err_frm_req                            can_top_level|clk_sys     SLE      Q       err_frm_req              0.218       1.751
memory_registers_inst.control_registers_reg_map_comp.mode_reg_comp.reg_value_r[10]           can_top_level|clk_sys     SLE      Q       drv_bus[475]             0.218       1.753
memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[8]      can_top_level|clk_sys     SLE      Q       txtb_sw_cmd_index[0]     0.218       1.803
memory_registers_inst.control_registers_reg_map_comp.tx_command_reg_comp.reg_value_r[9]      can_top_level|clk_sys     SLE      Q       tx_command[9]            0.218       1.901
can_core_inst.bit_destuffing_inst.dff_data_out_val_reg.output_fast                           can_top_level|clk_sys     SLE      Q       output_fast              0.218       1.905
memory_registers_inst.control_registers_reg_map_comp.tx_priority_reg_comp.reg_value_r[6]     can_top_level|clk_sys     SLE      Q       txtb_prorities_1[2]      0.218       1.946
memory_registers_inst.control_registers_reg_map_comp.tx_priority_reg_comp.reg_value_r[2]     can_top_level|clk_sys     SLE      Q       txtb_prorities_0[2]      0.218       1.952
==================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                          Starting                                                  Required          
Instance                                                                                  Reference                 Type     Pin     Net            Time         Slack
                                                                                          Clock                                                                       
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[0]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[1]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[2]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[3]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[4]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[5]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[6]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[7]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[8]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[9]     can_top_level|clk_sys     SLE      EN      un1_enable     9.873        1.646
======================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.127
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.873

    - Propagation time:                      8.227
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     1.646

    Number of logic level(s):                13
    Starting point:                          prescaler_inst.trigger_generator_inst.rx_trig_req_q_fast / Q
    Ending point:                            can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[0] / EN
    The start point is clocked by            can_top_level|clk_sys [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
    The end   point is clocked by            can_top_level|clk_sys [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK

Instance / Net                                                                                                           Pin      Pin               Arrival     No. of    
Name                                                                                                            Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
prescaler_inst.trigger_generator_inst.rx_trig_req_q_fast                                                        SLE      Q        Out     0.218     0.218 r     -         
rx_trig_req_q_fast                                                                                              Net      -        -       0.118     -           1         
can_core_inst.trigger_mux_inst.un3_pc_rx_trigger_0_a2                                                           CFG2     B        In      -         0.336 r     -         
can_core_inst.trigger_mux_inst.un3_pc_rx_trigger_0_a2                                                           CFG2     Y        Out     0.083     0.419 r     -         
test_probe_c[0]                                                                                                 Net      -        -       0.949     -           62        
can_core_inst.protocol_control_inst.protocol_control_fsm_inst.curr_state_RNIBP2A1[24]                           CFG4     D        In      -         1.368 r     -         
can_core_inst.protocol_control_inst.protocol_control_fsm_inst.curr_state_RNIBP2A1[24]                           CFG4     Y        Out     0.168     1.535 r     -         
sp_control_switch_data                                                                                          Net      -        -       0.563     -           4         
can_core_inst.protocol_control_inst.protocol_control_fsm_inst.un3_switch_to_ssp                                 CFG4     B        In      -         2.099 r     -         
can_core_inst.protocol_control_inst.protocol_control_fsm_inst.un3_switch_to_ssp                                 CFG4     Y        Out     0.083     2.182 r     -         
un3_switch_to_ssp_i                                                                                             Net      -        -       0.609     -           7         
prescaler_inst.segment_end_detector_inst.un2_nbt_tq_active_0_sx                                                 CFG4     C        In      -         2.791 r     -         
prescaler_inst.segment_end_detector_inst.un2_nbt_tq_active_0_sx                                                 CFG4     Y        Out     0.132     2.923 f     -         
un2_nbt_tq_active_0_sx                                                                                          Net      -        -       0.124     -           2         
prescaler_inst.segment_end_detector_inst.un2_nbt_tq_active_0                                                    CFG4     C        In      -         3.047 f     -         
prescaler_inst.segment_end_detector_inst.un2_nbt_tq_active_0                                                    CFG4     Y        Out     0.130     3.177 r     -         
un2_tq_edge                                                                                                     Net      -        -       0.796     -           25        
prescaler_inst.bit_segment_meter_dbt_inst.un8_exit_segm_regular_tseg1_d_xx_d_RNIL6296                           CFG4     D        In      -         3.973 r     -         
prescaler_inst.bit_segment_meter_dbt_inst.un8_exit_segm_regular_tseg1_d_xx_d_RNIL6296                           CFG4     Y        Out     0.232     4.205 r     -         
un8_exit_segm_regular_tseg1_1_1                                                                                 Net      -        -       0.118     -           1         
prescaler_inst.bit_segment_meter_dbt_inst.un5_exit_ph2_immediate_s_0_RNI1OODS                                   CFG3     B        In      -         4.323 r     -         
prescaler_inst.bit_segment_meter_dbt_inst.un5_exit_ph2_immediate_s_0_RNI1OODS                                   CFG3     Y        Out     0.083     4.406 r     -         
exit_segm_req_dbt                                                                                               Net      -        -       0.124     -           2         
prescaler_inst.segment_end_detector_inst.un2_segm_end_dbt_valid_0_RNIRVBJ81                                     CFG4     B        In      -         4.530 r     -         
prescaler_inst.segment_end_detector_inst.un2_segm_end_dbt_valid_0_RNIRVBJ81                                     CFG4     Y        Out     0.088     4.618 f     -         
g0_sx_1                                                                                                         Net      -        -       0.124     -           2         
prescaler_inst.segment_end_detector_inst.un1_h_sync_valid_i_rep1_RNI2SI491_0                                    CFG4     D        In      -         4.742 f     -         
prescaler_inst.segment_end_detector_inst.un1_h_sync_valid_i_rep1_RNI2SI491_0                                    CFG4     Y        Out     0.192     4.933 f     -         
g0_sx                                                                                                           Net      -        -       0.118     -           1         
prescaler_inst.segment_end_detector_inst.un1_h_sync_valid_i_rep1_RNIC2T473                                      CFG4     D        In      -         5.051 f     -         
prescaler_inst.segment_end_detector_inst.un1_h_sync_valid_i_rep1_RNIC2T473                                      CFG4     Y        Out     0.232     5.283 r     -         
segm_end                                                                                                        Net      -        -       0.623     -           8         
prescaler_inst.trigger_generator_inst.tx_trigger_0                                                              CFG4     C        In      -         5.906 r     -         
prescaler_inst.trigger_generator_inst.tx_trigger_0                                                              CFG4     Y        Out     0.148     6.054 r     -         
tx_trigger                                                                                                      Net      -        -       0.948     -           20        
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_down_proc\.un1_enable_0_N_2L1     CFG4     B        In      -         7.002 r     -         
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_down_proc\.un1_enable_0_N_2L1     CFG4     Y        Out     0.088     7.090 f     -         
un1_enable_0_N_2L1                                                                                              Net      -        -       0.118     -           1         
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_down_proc\.un1_enable_0           CFG4     C        In      -         7.208 f     -         
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_down_proc\.un1_enable_0           CFG4     Y        Out     0.130     7.338 r     -         
un1_enable                                                                                                      Net      -        -       0.889     -           32        
can_core_inst.protocol_control_inst.tx_shift_reg_inst.tx_shift_reg_inst.shift_regs[0]                           SLE      EN       In      -         8.227 r     -         
==========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.354 is 2.133(25.5%) logic and 6.221(74.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:29s; Memory used current: 386MB peak: 386MB)


Finished timing report (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:29s; Memory used current: 386MB peak: 386MB)

---------------------------------------
Resource Usage Report for can_top_level 

Mapping to part: mpf300tfcg1152-1
Cell usage:
CLKINT          1 use
CFG1           14 uses
CFG2           437 uses
CFG3           798 uses
CFG4           1698 uses

Carry cells:
ARI1            520 uses - used for arithmetic functions
ARI1            73 uses - used for Wide-Mux implementation
Total ARI1      593 uses


Sequential Cells: 
SLE            1175 uses

DSP Blocks:    0 of 924 (0%)

I/O ports: 161
I/O primitives: 155
INBUF          117 uses
OUTBUF         38 uses


Global Clock Buffers: 1

RAM/ROM usage summary
Total Block RAMs (RAM64x12) : 19 of 2772 (0%)

Total LUTs:    3540

Extra resources required for RAM and MACC_PA interface logic during P&R:

RAM64X12 Interface Logic : SLEs = 228; LUTs = 228;
RAM1K20  Interface Logic : SLEs = 0; LUTs = 0;
MACC_PA     Interface Logic : SLEs = 0; LUTs = 0;
MACC_PA_BC_ROM     Interface Logic : SLEs = 0; LUTs = 0;

Total number of SLEs after P&R:  1175 + 228 + 0 + 0 = 1403;
Total number of LUTs after P&R:  3540 + 228 + 0 + 0 = 3768;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:29s; Memory used current: 386MB peak: 386MB)

Process took 0h:00m:32s realtime, 0h:00m:29s cputime
# Fri Jul 15 21:03:06 2022

###########################################################]