SmartTime Version 2022.1.0.10
Microsemi Corporation - Microsemi Libero Software Release v2022.1 (Version 2022.1.0.10)
Date: Mon Jul 18 09:52:00 2022
Design |
ctu_can_fd_libero_top |
Family |
PolarFire |
Die |
MPF300TS |
Package |
FCG1152 |
Temperature Range |
-40 - 100 C |
Voltage Range |
0.97 - 1.03 V |
Speed Grade |
-1 |
Coverage Summary
Type of check |
Constrained |
UnConstrained |
Total |
Setup |
21441 |
1125 |
22566 |
Recovery |
11251 |
2 |
11253 |
Output Setup |
0 |
35 |
35 |
Total Setup |
32692 |
1162 |
33854 |
Hold |
21441 |
1125 |
22566 |
Removal |
11251 |
2 |
11253 |
Output Hold |
0 |
35 |
35 |
Total Hold |
32692 |
1162 |
33854 |
Clock domain:
SYS_CLK
Type of check |
Constrained |
UnConstrained |
Total |
Setup |
21441 |
1125 |
22566 |
Recovery |
11251 |
2 |
11253 |
Output Setup |
0 |
35 |
35 |
Total Setup |
32692 |
1162 |
33854 |
Hold |
21441 |
1125 |
22566 |
Removal |
11251 |
2 |
11253 |
Output Hold |
0 |
35 |
35 |
Total Hold |
32692 |
1162 |
33854 |
Enhancement Suggestions
- Max input delay constraint missing on ports:
- adress[10]
- adress[11]
- adress[2]
- adress[3]
- adress[4]
- adress[5]
- adress[6]
- adress[7]
- adress[8]
- adress[9]
- can_rx
- data_in[0]
- data_in[10]
- data_in[11]
- data_in[12]
- data_in[13]
- data_in[14]
- data_in[15]
- data_in[16]
- data_in[17]
- data_in[18]
- data_in[19]
- data_in[1]
- data_in[20]
- data_in[21]
- data_in[22]
- data_in[23]
- data_in[24]
- data_in[25]
- data_in[26]
- data_in[27]
- data_in[28]
- data_in[29]
- data_in[2]
- data_in[30]
- data_in[31]
- data_in[3]
- data_in[4]
- data_in[5]
- data_in[6]
- data_in[7]
- data_in[8]
- data_in[9]
- res_n
- sbe[0]
- sbe[1]
- sbe[2]
- sbe[3]
- scs
- srd
- swr
- timestamp[0]
- timestamp[10]
- timestamp[11]
- timestamp[12]
- timestamp[13]
- timestamp[14]
- timestamp[15]
- timestamp[16]
- timestamp[17]
- timestamp[18]
- timestamp[19]
- timestamp[1]
- timestamp[20]
- timestamp[21]
- timestamp[22]
- timestamp[23]
- timestamp[24]
- timestamp[25]
- timestamp[26]
- timestamp[27]
- timestamp[28]
- timestamp[29]
- timestamp[2]
- timestamp[30]
- timestamp[31]
- timestamp[32]
- timestamp[33]
- timestamp[34]
- timestamp[35]
- timestamp[36]
- timestamp[37]
- timestamp[38]
- timestamp[39]
- timestamp[3]
- timestamp[40]
- timestamp[41]
- timestamp[42]
- timestamp[43]
- timestamp[44]
- timestamp[45]
- timestamp[46]
- timestamp[47]
- timestamp[48]
- timestamp[49]
- timestamp[4]
- timestamp[50]
- timestamp[51]
- timestamp[52]
- timestamp[53]
- Min input delay constraint missing on ports:
- adress[10]
- adress[11]
- adress[2]
- adress[3]
- adress[4]
- adress[5]
- adress[6]
- adress[7]
- adress[8]
- adress[9]
- can_rx
- data_in[0]
- data_in[10]
- data_in[11]
- data_in[12]
- data_in[13]
- data_in[14]
- data_in[15]
- data_in[16]
- data_in[17]
- data_in[18]
- data_in[19]
- data_in[1]
- data_in[20]
- data_in[21]
- data_in[22]
- data_in[23]
- data_in[24]
- data_in[25]
- data_in[26]
- data_in[27]
- data_in[28]
- data_in[29]
- data_in[2]
- data_in[30]
- data_in[31]
- data_in[3]
- data_in[4]
- data_in[5]
- data_in[6]
- data_in[7]
- data_in[8]
- data_in[9]
- res_n
- sbe[0]
- sbe[1]
- sbe[2]
- sbe[3]
- scs
- srd
- swr
- timestamp[0]
- timestamp[10]
- timestamp[11]
- timestamp[12]
- timestamp[13]
- timestamp[14]
- timestamp[15]
- timestamp[16]
- timestamp[17]
- timestamp[18]
- timestamp[19]
- timestamp[1]
- timestamp[20]
- timestamp[21]
- timestamp[22]
- timestamp[23]
- timestamp[24]
- timestamp[25]
- timestamp[26]
- timestamp[27]
- timestamp[28]
- timestamp[29]
- timestamp[2]
- timestamp[30]
- timestamp[31]
- timestamp[32]
- timestamp[33]
- timestamp[34]
- timestamp[35]
- timestamp[36]
- timestamp[37]
- timestamp[38]
- timestamp[39]
- timestamp[3]
- timestamp[40]
- timestamp[41]
- timestamp[42]
- timestamp[43]
- timestamp[44]
- timestamp[45]
- timestamp[46]
- timestamp[47]
- timestamp[48]
- timestamp[49]
- timestamp[4]
- timestamp[50]
- timestamp[51]
- timestamp[52]
- timestamp[53]
- Max output delay constraint missing on ports:
- can_tx
- data_out[0]
- data_out[10]
- data_out[11]
- data_out[12]
- data_out[13]
- data_out[14]
- data_out[15]
- data_out[16]
- data_out[17]
- data_out[18]
- data_out[19]
- data_out[1]
- data_out[20]
- data_out[21]
- data_out[22]
- data_out[23]
- data_out[24]
- data_out[25]
- data_out[26]
- data_out[27]
- data_out[28]
- data_out[29]
- data_out[2]
- data_out[30]
- data_out[31]
- data_out[3]
- data_out[4]
- data_out[5]
- data_out[6]
- data_out[7]
- data_out[8]
- data_out[9]
- int_Z
- res_n_out
- Min output delay constraint missing on ports:
- can_tx
- data_out[0]
- data_out[10]
- data_out[11]
- data_out[12]
- data_out[13]
- data_out[14]
- data_out[15]
- data_out[16]
- data_out[17]
- data_out[18]
- data_out[19]
- data_out[1]
- data_out[20]
- data_out[21]
- data_out[22]
- data_out[23]
- data_out[24]
- data_out[25]
- data_out[26]
- data_out[27]
- data_out[28]
- data_out[29]
- data_out[2]
- data_out[30]
- data_out[31]
- data_out[3]
- data_out[4]
- data_out[5]
- data_out[6]
- data_out[7]
- data_out[8]
- data_out[9]
- int_Z
- res_n_out
- Setup unconstrained for the following pins:
- can_top_level_inst/bus_sampling_inst/can_rx_sig_sync_inst/rff:D
- can_top_level_inst/can_core_inst/bus_traffic_ctrs_gen.bus_traffic_counters_inst/rx_ctr_reg_rst_inst/rx_shift_res_reg_inst/reg_q:D
- can_top_level_inst/can_core_inst/bus_traffic_ctrs_gen.bus_traffic_counters_inst/tx_ctr_reg_rst_inst/rx_shift_res_reg_inst/reg_q:D
- can_top_level_inst/can_core_inst/protocol_control_inst/protocol_control_fsm_inst/drv_bus_off_reset_q:D
- can_top_level_inst/int_manager_inst/int_module_gen.0.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.0.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.0.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.0.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.1.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.1.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.1.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.1.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.10.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.10.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.10.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.10.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.11.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.11.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.11.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.11.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.2.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.2.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.2.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.2.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.3.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.3.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.3.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.3.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.4.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.4.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.4.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.4.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.5.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.5.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.5.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.5.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.6.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.6.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.6.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.6.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.7.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.7.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.7.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.7.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.8.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.8.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.8.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.8.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.9.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.9.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.9.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.9.int_module_inst/int_mask_i:EN
- can_top_level_inst/memory_registers_inst/control_registers_cs_reg:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[0]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[0]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[10]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[10]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[11]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[11]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[12]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[12]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[13]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[13]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[14]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[14]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[15]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[15]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[16]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[16]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[17]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[17]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[18]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[18]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[19]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[19]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[1]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[1]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[20]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[20]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[21]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[21]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[22]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[22]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[23]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[23]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[24]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[24]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[25]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[25]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[26]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[26]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[27]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[27]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[28]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[28]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[2]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[2]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[3]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[3]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[4]:D
- Recovery unconstrained for the following pins:
- can_top_level_inst/rst_sync_inst/rff:ALn
- can_top_level_inst/rst_sync_inst/rst:ALn
- Hold unconstrained for the following pins:
- can_top_level_inst/bus_sampling_inst/can_rx_sig_sync_inst/rff:D
- can_top_level_inst/can_core_inst/bus_traffic_ctrs_gen.bus_traffic_counters_inst/rx_ctr_reg_rst_inst/rx_shift_res_reg_inst/reg_q:D
- can_top_level_inst/can_core_inst/bus_traffic_ctrs_gen.bus_traffic_counters_inst/tx_ctr_reg_rst_inst/rx_shift_res_reg_inst/reg_q:D
- can_top_level_inst/can_core_inst/protocol_control_inst/protocol_control_fsm_inst/drv_bus_off_reset_q:D
- can_top_level_inst/int_manager_inst/int_module_gen.0.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.0.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.0.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.0.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.1.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.1.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.1.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.1.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.10.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.10.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.10.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.10.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.11.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.11.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.11.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.11.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.2.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.2.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.2.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.2.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.3.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.3.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.3.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.3.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.4.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.4.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.4.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.4.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.5.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.5.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.5.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.5.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.6.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.6.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.6.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.6.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.7.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.7.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.7.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.7.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.8.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.8.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.8.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.8.int_module_inst/int_mask_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.9.int_module_inst/int_ena_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.9.int_module_inst/int_ena_i:EN
- can_top_level_inst/int_manager_inst/int_module_gen.9.int_module_inst/int_mask_i:D
- can_top_level_inst/int_manager_inst/int_module_gen.9.int_module_inst/int_mask_i:EN
- can_top_level_inst/memory_registers_inst/control_registers_cs_reg:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[0]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[0]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[10]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[10]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[11]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[11]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[12]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[12]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[13]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[13]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[14]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[14]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[15]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[15]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[16]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[16]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[17]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[17]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[18]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[18]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[19]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[19]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[1]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[1]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[20]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[20]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[21]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[21]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[22]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[22]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[23]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[23]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[24]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[24]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[25]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[25]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[26]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[26]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[27]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[27]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[28]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[28]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[2]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[2]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[3]:D
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[3]:EN
- can_top_level_inst/memory_registers_inst/control_registers_reg_map_comp/FILTER_A_MASK_present_gen_t.filter_a_mask_reg_comp/reg_value_r[4]:D
- Removal unconstrained for the following pins:
- can_top_level_inst/rst_sync_inst/rff:ALn
- can_top_level_inst/rst_sync_inst/rst:ALn
Input to Output
Type of check |
Constrained |
UnConstrained |
Total |
Output Setup |
0 |
0 |
0 |
Output Hold |
0 |
0 |
0 |