Project Settings
Project Name ctu_can_fd_libero_top_syn Device Name synthesis: Microchip PolarFire : MPF300T
Implementation Name synthesis Top Module ctu_can_fd_rtl.ctu_can_fd_libero_top
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 354 193 0 - 00m:17s - 18.07.22
9:35
(premap)Complete 31 1 0 0m:11s 0m:12s 366MB 18.07.22
9:35
(fpga_mapper)Complete 51 8 0 01m:25s 01m:27s 394MB 18.07.22
9:36
Multi-srs Generator Complete00m:02s18.07.22
9:35

Area Summary
Carry Cells 6234 Sequential Cells 11541
DSP Blocks (dsp_used) 0 I/O Cells 151
Global Clock Buffers 2 LUTs (total_luts) 13244

Timing Summary
Clock NameReq FreqEst FreqSlack
SYS_CLK100.0 MHz99.4 MHz-0.056

Optimizations Summary
Combined Clock Conversion 1 / 0

Compile Points Summary
NameStatusReasonReal TimeCPU Time
inf_ram_wrapper_32_128_12_true_trueUnchanged-0h:00m:35s0h:00m:33s
can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0Unchanged-0h:00m:26s0h:00m:23s
ctu_can_fd_libero_topUnchanged-0h:00m:03s0h:00m:03s
can_top_level_128_8_true_true_true_true_true_true_true_63_true_1RemappedDesign changed0h:01m:07s0h:01m:06s