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00043 #include "board.h"
00044 #include "sdramc_at32ap7000.h"
00045 #include "gpio.h"
00046
00047 static void sdramc_enable_muxed_pins(void)
00048 {
00049 volatile avr32_hmatrix_t *hmatrix = &AVR32_HMATRIX;
00050
00051
00052 hmatrix->sfr[4] |= 0x0002;
00053 hmatrix->sfr[4] |= 0x0100;
00054
00055 static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
00056 {
00057
00058 {AVR32_EBI_DATA_16_PIN, AVR32_EBI_DATA_16_FUNCTION },
00059 {AVR32_EBI_DATA_17_PIN, AVR32_EBI_DATA_17_FUNCTION },
00060 {AVR32_EBI_DATA_18_PIN, AVR32_EBI_DATA_18_FUNCTION },
00061 {AVR32_EBI_DATA_19_PIN, AVR32_EBI_DATA_19_FUNCTION },
00062 {AVR32_EBI_DATA_20_PIN, AVR32_EBI_DATA_20_FUNCTION },
00063 {AVR32_EBI_DATA_21_PIN, AVR32_EBI_DATA_21_FUNCTION },
00064 {AVR32_EBI_DATA_22_PIN, AVR32_EBI_DATA_22_FUNCTION },
00065 {AVR32_EBI_DATA_23_PIN, AVR32_EBI_DATA_23_FUNCTION },
00066 {AVR32_EBI_DATA_24_PIN, AVR32_EBI_DATA_24_FUNCTION },
00067 {AVR32_EBI_DATA_25_PIN, AVR32_EBI_DATA_25_FUNCTION },
00068 {AVR32_EBI_DATA_26_PIN, AVR32_EBI_DATA_26_FUNCTION },
00069 {AVR32_EBI_DATA_27_PIN, AVR32_EBI_DATA_27_FUNCTION },
00070 {AVR32_EBI_DATA_28_PIN, AVR32_EBI_DATA_28_FUNCTION },
00071 {AVR32_EBI_DATA_29_PIN, AVR32_EBI_DATA_29_FUNCTION },
00072 {AVR32_EBI_DATA_30_PIN, AVR32_EBI_DATA_30_FUNCTION },
00073 {AVR32_EBI_DATA_31_PIN, AVR32_EBI_DATA_31_FUNCTION }
00074 };
00075
00076 gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
00077 };
00078
00079 static void sdram_delay(int tics)
00080 {
00081 int i, loop_limit;
00082
00083 loop_limit = tics * 20;
00084
00085 for (i=0; i<loop_limit;i++);
00086
00087 }
00088
00089 void sdramc_init(unsigned long hsb_hz)
00090 {
00091
00092 volatile avr32_sdramc_t *sdramc = &AVR32_SDRAMC;
00093 volatile U32 *sdram = (void *) BOARD_SDRAM_BASE;
00094 U32 i;
00095
00096 sdramc_enable_muxed_pins();
00097
00098
00099 sdramc->cr = ( (SDRAM_COL_BITS - 8) << AVR32_SDRAMC_CR_NC ) |
00100 ( (SDRAM_ROW_BITS - 11) << AVR32_SDRAMC_CR_NR ) |
00101 ( (SDRAM_BANK_BITS - 1) << AVR32_SDRAMC_CR_NB ) |
00102 ( SDRAM_CAS << AVR32_SDRAMC_CR_CAS ) |
00103 ( SDRAM_TWR << AVR32_SDRAMC_CR_TWR ) |
00104 ( SDRAM_TRC << AVR32_SDRAMC_CR_TRC ) |
00105 ( SDRAM_TRP << AVR32_SDRAMC_CR_TRP ) |
00106 ( SDRAM_TRCD << AVR32_SDRAMC_CR_TRCD ) |
00107 ( SDRAM_TRAS << AVR32_SDRAMC_CR_TRAS ) |
00108 ( SDRAM_TXSR << AVR32_SDRAMC_CR_TXSR );
00109
00110 sdram_delay(200);
00111
00112
00113 sdramc->mr = AVR32_SDRAMC_MR_MODE_BANKS_PRECHARGE;
00114 sdramc->mr;
00115 sdram[0] = 0;
00116
00117
00118 sdramc->mr = AVR32_SDRAMC_MR_MODE_AUTO_REFRESH;
00119 sdramc->mr;
00120 for (i = 0; i < 8; i++)
00121 sdram[0] = 0;
00122
00123
00124
00125
00126
00127
00128 sdramc->mr = AVR32_SDRAMC_MR_MODE_LOAD_MODE;
00129 sdramc->mr;
00130 sdram[0x020] = 0;
00131
00132
00133 sdramc->mr;
00134 sdramc->mr = AVR32_SDRAMC_MR_MODE_NORMAL;
00135 sdramc->mr;
00136 sdram[0] = 0;
00137
00138
00139 sdramc->tr = ( ( 156 * (hsb_hz / 1000) ) / 10000 );
00140 }
00141