00001 /*This file is prepared for Doxygen automatic documentation generation.*/ 00017 /* Copyright (C) 2006-2008, Atmel Corporation All rights reserved. 00018 * 00019 * Redistribution and use in source and binary forms, with or without 00020 * modification, are permitted provided that the following conditions are met: 00021 * 00022 * 1. Redistributions of source code must retain the above copyright notice, 00023 * this list of conditions and the following disclaimer. 00024 * 00025 * 2. Redistributions in binary form must reproduce the above copyright notice, 00026 * this list of conditions and the following disclaimer in the documentation 00027 * and/or other materials provided with the distribution. 00028 * 00029 * 3. The name of ATMEL may not be used to endorse or promote products derived 00030 * from this software without specific prior written permission. 00031 * 00032 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED 00033 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 00034 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND 00035 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, 00036 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00037 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00038 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 00039 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00040 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 00041 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00042 */ 00043 00044 00045 #include <avr32/io.h> 00046 #include "compiler.h" 00047 #include "preprocessor.h" 00048 #include "intc.h" 00049 00050 00052 extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS]; 00053 00056 #if __GNUC__ 00057 #define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ 00058 static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; 00059 #elif __ICCAVR32__ 00060 #define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ 00061 static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; 00062 #endif 00063 MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~); 00064 #undef DECL_INT_LINE_HANDLER_TABLE 00065 00068 static const struct 00069 { 00070 unsigned int num_irqs; 00071 volatile __int_handler *_int_line_handler_table; 00072 } _int_handler_table[AVR32_INTC_NUM_INT_GRPS] = 00073 { 00074 #define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \ 00075 {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP}, 00076 MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~) 00077 #undef INSERT_INT_LINE_HANDLER_TABLE 00078 }; 00079 00080 00085 #if __GNUC__ 00086 __attribute__((__interrupt__)) 00087 #elif __ICCAVR32__ 00088 __interrupt 00089 #endif 00090 static void _unhandled_interrupt(void) 00091 { 00092 // Catch unregistered interrupts. 00093 while (TRUE); 00094 } 00095 00096 00106 __int_handler _get_interrupt_handler(unsigned int int_lev) 00107 { 00108 // ICR3 is mapped first, ICR0 last. 00109 // Code in exception.S puts int_lev in R12 which is used by AVR32-GCC to pass 00110 // a single argument to a function. 00111 unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_lev]; 00112 unsigned int int_req = AVR32_INTC.irr[int_grp]; 00113 00114 // As an interrupt may disappear while it is being fetched by the CPU 00115 // (spurious interrupt caused by a delayed response from an MCU peripheral to 00116 // an interrupt flag clear or interrupt disable instruction), check if there 00117 // are remaining interrupt lines to process. 00118 // If a spurious interrupt occurs, the status register (SR) contains an 00119 // execution mode and interrupt level masks corresponding to a level 0 00120 // interrupt, whatever the interrupt priority level causing the spurious 00121 // event. This behavior has been chosen because a spurious interrupt has not 00122 // to be a priority one and because it may not cause any trouble to other 00123 // interrupts. 00124 // However, these spurious interrupts place the hardware in an unstable state 00125 // and could give problems in other/future versions of the CPU, so the 00126 // software has to be written so that they never occur. The only safe way of 00127 // achieving this is to always clear or disable peripheral interrupts with the 00128 // following sequence: 00129 // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR. 00130 // 2: Perform the bus access to the peripheral register that clears or 00131 // disables the interrupt. 00132 // 3: Wait until the interrupt has actually been cleared or disabled by the 00133 // peripheral. This is usually performed by reading from a register in the 00134 // same peripheral (it DOES NOT have to be the same register that was 00135 // accessed in step 2, but it MUST be in the same peripheral), what takes 00136 // bus system latencies into account, but peripheral internal latencies 00137 // (generally 0 cycle) also have to be considered. 00138 // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR. 00139 // Note that steps 1 and 4 are useless inside interrupt handlers as the 00140 // corresponding interrupt level is automatically masked by IxM (unless IxM is 00141 // explicitly cleared by the software). 00142 // 00143 // Get the right IRQ handler. 00144 // 00145 // If several interrupt lines are active in the group, the interrupt line with 00146 // the highest number is selected. This is to be coherent with the 00147 // prioritization of interrupt groups performed by the hardware interrupt 00148 // controller. 00149 // 00150 // If no handler has been registered for the pending interrupt, 00151 // _unhandled_interrupt will be selected thanks to the initialization of 00152 // _int_line_handler_table_x by INTC_init_interrupts. 00153 // 00154 // exception.S will provide the interrupt handler with a clean interrupt stack 00155 // frame, with nothing more pushed onto the stack. The interrupt handler must 00156 // manage the `rete' instruction, what can be done thanks to pure assembly, 00157 // inline assembly or the `__attribute__((__interrupt__))' C function 00158 // attribute. 00159 return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL; 00160 } 00161 00162 00163 void INTC_init_interrupts(void) 00164 { 00165 unsigned int int_grp, int_req; 00166 00167 // For all interrupt groups, 00168 for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++) 00169 { 00170 // For all interrupt request lines of each group, 00171 for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++) 00172 { 00173 // Assign _unhandled_interrupt as default interrupt handler. 00174 _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt; 00175 } 00176 00177 // Set the interrupt group priority register to its default value. 00178 // By default, all interrupt groups are linked to the interrupt priority 00179 // level 0 and to the interrupt vector _int0. 00180 AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0]; 00181 } 00182 } 00183 00184 00185 void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev) 00186 { 00187 // Determine the group of the IRQ. 00188 unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP; 00189 00190 // Store in _int_line_handler_table_x the pointer to the interrupt handler, so 00191 // that _get_interrupt_handler can retrieve it when the interrupt is vectored. 00192 _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler; 00193 00194 // Program the corresponding IPRX register to set the interrupt priority level 00195 // and the interrupt vector offset that will be fetched by the core interrupt 00196 // system. 00197 // NOTE: The _intx functions are intermediate assembly functions between the 00198 // core interrupt system and the user interrupt handler. 00199 AVR32_INTC.ipr[int_grp] = ipr_val[int_lev & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)]; 00200 }