//Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp
// Spec Reference: dsp32shift signbits dregs
# mach: bfin

.include "testutils.inc"
	start





imm32 r0, 0x88880000;
imm32 r1, 0x34560001;
imm32 r2, 0x08000002;
imm32 r3, 0x08000003;
imm32 r4, 0x08000004;
imm32 r5, 0x08000005;
imm32 r6, 0x08000006;
imm32 r7, 0x08000007;
R7.L = SIGNBITS R0;
R1.L = SIGNBITS R0;
R2.L = SIGNBITS R0;
R3.L = SIGNBITS R0;
R4.L = SIGNBITS R0;
R5.L = SIGNBITS R0;
R6.L = SIGNBITS R0;
R0.L = SIGNBITS R0;
CHECKREG r0, 0x88880000;
CHECKREG r1, 0x34560000;
CHECKREG r2, 0x08000000;
CHECKREG r3, 0x08000000;
CHECKREG r4, 0x08000000;
CHECKREG r5, 0x08000000;
CHECKREG r6, 0x08000000;
CHECKREG r7, 0x08000000;

imm32 r0, 0x9999001E;
imm32 r1, 0x0000001E;
imm32 r2, 0x0000001E;
imm32 r3, 0x0000001E;
imm32 r4, 0x0000001E;
imm32 r5, 0x0000001E;
imm32 r6, 0x0000001E;
imm32 r7, 0x0000001E;
R0.L = SIGNBITS R1;
R7.L = SIGNBITS R1;
R2.L = SIGNBITS R1;
R3.L = SIGNBITS R1;
R4.L = SIGNBITS R1;
R5.L = SIGNBITS R1;
R6.L = SIGNBITS R1;
R1.L = SIGNBITS R1;
CHECKREG r0, 0x9999001A;
CHECKREG r1, 0x0000001A;
CHECKREG r2, 0x0000001A;
CHECKREG r3, 0x0000001A;
CHECKREG r4, 0x0000001A;
CHECKREG r5, 0x0000001A;
CHECKREG r6, 0x0000001A;
CHECKREG r7, 0x0000001A;


imm32 r0, 0x0aaae001;
imm32 r1, 0x0000e001;
imm32 r2, 0xaaaa000f;
imm32 r3, 0x0a00e003;
imm32 r4, 0x00a0e004;
imm32 r5, 0x00a0e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0b00e007;
R0.L = SIGNBITS R2;
R1.L = SIGNBITS R2;
R7.L = SIGNBITS R2;
R3.L = SIGNBITS R2;
R4.L = SIGNBITS R2;
R5.L = SIGNBITS R2;
R6.L = SIGNBITS R2;
R2.L = SIGNBITS R2;
CHECKREG r0, 0x0AAA0000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xAAAA0000;
CHECKREG r3, 0x0A000000;
CHECKREG r4, 0x00A00000;
CHECKREG r5, 0x00A00000;
CHECKREG r6, 0x0A000000;
CHECKREG r7, 0x0B000000;

imm32 r0, 0x0b00f001;
imm32 r1, 0x0a00f001;
imm32 r2, 0x0b00f002;
imm32 r3, 0xbbbb0010;
imm32 r4, 0x0b00f004;
imm32 r5, 0x0b00f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x00b0f007;
R0.L = SIGNBITS R3;
R1.L = SIGNBITS R3;
R2.L = SIGNBITS R3;
R7.L = SIGNBITS R3;
R4.L = SIGNBITS R3;
R5.L = SIGNBITS R3;
R6.L = SIGNBITS R3;
R3.L = SIGNBITS R3;
CHECKREG r0, 0x0B000000;
CHECKREG r1, 0x0A000000;
CHECKREG r2, 0x0B000000;
CHECKREG r3, 0xBBBB0000;
CHECKREG r4, 0x0B000000;
CHECKREG r5, 0x0B000000;
CHECKREG r6, 0x0B000000;
CHECKREG r7, 0x00B00000;

imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0xcccc0000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = SIGNBITS R4;
R1.L = SIGNBITS R4;
R2.L = SIGNBITS R4;
R3.L = SIGNBITS R4;
R7.L = SIGNBITS R4;
R5.L = SIGNBITS R4;
R6.L = SIGNBITS R4;
R4.L = SIGNBITS R4;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020001;
CHECKREG r3, 0x00030001;
CHECKREG r4, 0xCCCC0001;
CHECKREG r5, 0x00050001;
CHECKREG r6, 0x00060001;
CHECKREG r7, 0x00070001;

imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xdddd0000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = SIGNBITS R5;
R1.L = SIGNBITS R5;
R2.L = SIGNBITS R5;
R3.L = SIGNBITS R5;
R4.L = SIGNBITS R5;
R7.L = SIGNBITS R5;
R6.L = SIGNBITS R5;
R5.L = SIGNBITS R5;
CHECKREG r0, 0xA0010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0xA0020001;
CHECKREG r3, 0xA0030001;
CHECKREG r4, 0xA0040001;
CHECKREG r5, 0xDDDD0001;
CHECKREG r6, 0xA0060001;
CHECKREG r7, 0xA0070001;


imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xeeee0000;
imm32 r7, 0xb0070000;
R0.L = SIGNBITS R6;
R1.L = SIGNBITS R6;
R2.L = SIGNBITS R6;
R3.L = SIGNBITS R6;
R4.L = SIGNBITS R6;
R5.L = SIGNBITS R6;
R7.L = SIGNBITS R6;
R6.L = SIGNBITS R6;
CHECKREG r0, 0xB0010002;
CHECKREG r1, 0xB0010002;
CHECKREG r2, 0xB0020002;
CHECKREG r3, 0xB0030002;
CHECKREG r4, 0xB0040002;
CHECKREG r5, 0xB0050002;
CHECKREG r6, 0xEEEE0002;
CHECKREG r7, 0xB0070002;

imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xffff0000;
R0.L = SIGNBITS R7;
R1.L = SIGNBITS R7;
R2.L = SIGNBITS R7;
R3.L = SIGNBITS R7;
R4.L = SIGNBITS R7;
R5.L = SIGNBITS R7;
R6.L = SIGNBITS R7;
R7.L = SIGNBITS R7;

CHECKREG r0, 0xD001000F;
CHECKREG r1, 0xD001000F;
CHECKREG r2, 0xD002000F;
CHECKREG r3, 0xD003000F;
CHECKREG r4, 0xD004000F;
CHECKREG r5, 0xD005000F;
CHECKREG r6, 0xD006000F;
CHECKREG r7, 0xFFFF000F;
pass
