Project Name: Biquad IIR Filter Core

Specifications:

  • IIR filter with two poles and two zeros
  • Data width set by user
  • Coefficient width set by user up to 16 bits
  • Wishbone interface for read and write of filter coefficient registers
  • Multiple filters can be combined to form filters with more than two poles and zeros



    • Description:

    The difference equation for the biquad filter is:

    y[n] = b10*x[n] + b11*x[n-1] + b12*x[n-2] + a11*y[n-1] + a12*y[n-2]

    This equation is implemented as shown below:

    Specification in pdf format: biquad.pdf

    Synthesis:


    Synthesized with Synopsys FPGA Express version 2000.11-FE3.5.


    Current Status:


    Verilog source code available.


    Author & Maintainer:



    If you use this core please let me know.