Project Name: Bluetooth baseband controller
Preliminary architecture
Interfaces:
- RF interface Several interfaces have been checked such as JTAG and SPI but we are going to implement our standard interface and bild bridges around it for other interfaces
- CPU interface Wishbone SOC bus is going to be used to access the core. Two DMA channels (RX/TX) can be added
- HCI OpenCores USB and UART can be used. Messeges and control between host and Baseband are TBD
- Voice interface Standard PCM interface will be usedand internal codec will be implemented
- Clocks 1MHz, 13-20MHz (System clock)and 32KHz (low power mode)
RF generic interface:
- This interface should be generic and simple so that it can be bridged to any other RF interfaces
- The RF bridge will be responsible for mapping these signals into RF chip registers and signals according to specific RF chips interfaces
- Clocks
- SysClk : Out : System clock
- Clock frequency is TBD but a recommendation is to be
15-20MHz to accomodate any possible delay may be causes by
bridge state machines
- Any extra clocks needed by RF should be handled by the
RF bridge
- Register group
- Dout(8) : Out: 8 bit bus to write to RF register
- Din(8) : In : 8 bit bus to read from RF register
- Wr : Out: write signal
- Re : Out: read signal
- ReAck : In : Read acknowledge
- WrAck : Out: Write acknowledge
- (we need different buses for read and write because
JTAG interace can read and write at the same time)
- Data transfer
- TxEn : Out : Tx Enable
- TxRdy : in : Tx Ready (RF got the data bit from
TxData)
- Txdata: Out : Tx Data Bit
- RxEn : Out : Rx Enable
- RxRdy : in : Rx Ready (RF set the data bit to
RxData)
- Rxdata: Out : Rx Data Bit
- Hop selection
- Hop(7) : Out : 7 bit hop bus
- SetHop : Out : Load hop value to RF
Buffers:
- Tx and Rx buffers of the maximum packet sizes must be used at the RF side
- Tx Buffer will be flushed only when the transmitted packet has acknoledged.
- The buffers should be connected to the read/write and link state machines