(See change Log at bottom of page for changes/updates)

Description:

This is a pipeline floating point Add/Subtract unit compliant to IEEE 754. It has a 4 stage pipeline and can execute an add/sub every cycle.

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This design should be IEEE 754 single precision compliant. The following items might not be fully compliant or are not implemented:

• Underflow and Overflow are not checked
• INF and NaN are signaled on two separate output pins. The actual output of the unit might not contain an INF or NAN. (However inputs are properly decoded to determine if one of them is a INF or NAN).
• Denormalized inputs are not normalized
• Output sign might be incorrect for operations containing INF or NaN (I don't quite understand how it supposed to be :*)

• 4 cycle pipeline (easily extended to reduce cycle time but increase latency ...)
• Every cycle and add or subtract

• Utilizes about 321 CLBs
• 23nS cycle time in a VCS100 -4 (Virtex -4, the slowest in the Virtex group)
• About 7k Gates Equivalent

First version of the core is released. Included with the release is also a small test bench.

The core can be downloaded from OpenCores CVS via cvsweb or via cvsget (use fasu for module name)
 

To-Do

Things that need to be done

• Write more  test vectors
• Need a real testbench, somebody please write a C program that will generate 2 Single Prec. floating point numbers and predict the result of an add/sub.
• Fix Incompatibilities

I have been doing ASIC design, verification and synthesis for over 15 years. This core was an small exercise to refresh my memory how floating point numbers where represented in hardware and how a simple add/sub would work ....

I'd love to know if anyone will actually use this core. Please send me a note if you will !

Rudolf Usselmann rudi@opencores.org

Feel free to send me comments, suggestions and bug reports.

Change Log

7/4/2000 RU
- Initial Release