HDLC controller

Introduction

HDLC controller features

1. 8 bit parallel backend interface
2. use external RX and TX clocks
3. Start and end of frame pattern generation
4. Start and end of frame pattern checking
5. Idle pattern generation and detection (all ones)
5. a) Idle pattern is assumed only after the end of a frame which is signaled by an abort signal
6. Zero insertion
7. Abort pattern generation and checking
8. Address insertion and detection by software
9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used)
10. FIFO buffers and synchronization (External)
11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
12. Q.921, LAPB and LAPD compliant.
13. For complete specifications refer to spec document

System specifications and interfaces

Check the system spec and interaces or you can download the PS file or PDF file

Core top block diagram

Status

The VHDL code is ready in the opencores CVS. The code needs verification contact me if you are intrested in helping me.

Resource usage

Rx Channel Block: which includes HDLC Framing extraction, zero removal and conversion from serial to parallel.

Vendor	Device	Size	Frequency	Board Tested	Functional Test	Notes
Altera	EP20K100BC356-3	108 LCs	91.48MHz	-	-	No optimization was peroformed, using Quartus II

Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial.

Vendor	Device	Size	Frequency	Board Tested	Functional Test	Notes
Altera	EP20K100BC356-3	100 LCs	112.42MHz	-	-	No optimization was peroformed, using Quartus II

HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers.

Vendor	Device	Size	Frequencies (MHz)	Board Tested	Functional Test	Notes
Altera	EP20K100BC356-3	630 LCs, 2 ESBs	CLK_I=74.02,RxClk=101.86,TxClk=106.42	-	-	No optimization was peroformed, using Quartus II

Links

Maintainer(s):

Jamil Khatib

Author(s):

Jamil Khatib

Contact email:

Khatib@opencores.org_NOSPAM

Mailing-List:

cores@opencores.org_NOSPAM