News

2001.6.3 nnARM moved to Opencores

I have just got this account, and I will try to learn how to use CVS and other rules and procedures of Opencores. Now it is more convenient for anyone interested in this project to take part in it. Please refer to the Introduction page for what types of help we need.

2001.6.2 Some sections of documentation v1.10 are released

Because I will be busy in the following 2 weeks for other things, I can not find time to write the full documentation. However, I think a partial document is better than no documentation. A full version will be released later.

2001.5.30 I need help on memory system. Cache system and memory bus.

The memory and cache system of my design are not very suitable for this processor. Because I want to devote myself to the design of the processor itself, I have used a VERY SIMPLE model of cache and memory. Whoever can help me to develop a better model pleasecontact me

2001.5.29 It runs some complex asembly source code from ARM SDT 2.5

I used some assembly source code with ARM SDT 2.5. It runs very well and obtains good results. For more detail,please refer to TestBench

2001.5.24 The PC can now be used as a source and/or target register.

Because the PC is not a general register, when an instruction reaches the EXE and MEM stage, the current PC is ahead of the PC of the current instruction by 8 or 12 bytes. So it can not be read to the EXE stage as a general register. Therefore, it is read at the decoder stage and then adjusted the proper amount and at last sent to the EXE stage as an immediate value. For the case of a write to the PC, it is treated as a Branch instruction.

2001.5.23 Support for Multiply and Multiply-Accumulate (MUL, MLA)

These two instructions can do multiply and multiply and then add operations.

2001.5.21 Support for branch and branch with link

These two instructions change the PC, and the later can write the next instruction address to R14 for return from subrutine.

2001.5.20 Support for MRS and MSR instruction

These two instructions write CPSR/SPSR to and from general registers.

2001.5.17 Support for CPSR and SPSR read/write

The two registers (actually six registers,including cpsr spsr_fiq spsr_und spsr_svc spsr_irq spsr_abt) can now be read/written, and the pipeline can use the condition code from cpsr to decide if an instruction can be executed.

2001.5.16 Brand New Architecture and support for Load/Store

Since the last update a month ago, I am working hard to change the architecture of nnARM,the main reason is described as follows: When I started to develop this soft core,I thought that the ARM instruction set is very similar to the typical risc machine (such as DLX and MIPS.) Thus, I thought I could develop a RISC core to run various RISC instruction sets. This idea is not wrong for a typical RISC architecture, but it is wrong for ARM. When I pushed forward with the development, I found that the ARM instruction set is very different from typical RISC. It is difficult to run the ARM instruction set on it efficiently. So I designed a brand new architecture for ARM. And all functions that have been supported by the old architecture are also supported by the new architecture. At the same time, I added support for load and store instructions.

2001.4.17 Full Function ALU

A new full function ALU has been released. It can support all ALU operations in the ARM instruction set. Its documentation is online now.

2001.4.15 A new Barrel Shifter

I have written documentation for the first release of this synthesable soft core in the last week. Now, the documentation has been updated. I started to push forword with this project again tonight. I have written a new barrel shifter (in BarrelShift.v) and its test bench(in tb_BarrelShift.v). New documentation sections about the new Barrel Shifter are also online now.

2001.4.10 IT RUNS NOW!

After 2 weeks of hard work, the processor now can run the ADD Instruction, but I know that it does have some limitations: FIRST:the tomasulo structure still can not tell the decoder that an instruction has completed, so that the decoder can clear the register usage. SECOND:the ALUWrapper still can not read from the write bus,so it can only get results from within ALUWrapper, only from the other entry. Except the above two limitations,it runs fairly well.