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1.2
date	2002.07.07.11.14.55;	author yapzihe;	state dead;
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1.1
date	2002.06.28.22.04.40;	author yapzihe;	state Exp;
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1.2
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AVRASM ver. 1.30  CALC.ASM Sun Mar 17 14:05:28 2002


          .include "riscmcu.inc"
         
         ;***** I/O Register Definitions
         
          .equ	SREG	=$3f
          .equ	GIMSK	=$3b
          .equ	TIMSK	=$39
          .equ	TIFR	=$38
          .equ	MCUCR	=$35
          .equ	TCCR0	=$33
          .equ	TCNT0	=$32
         
          .equ	PORTB	=$18
          .equ	DDRB	=$17
          .equ	PINB	=$16
          .equ	PORTC	=$15
          .equ	DDRC	=$14
          .equ	PINC	=$13
          .equ	PORTD	=$12
          .equ	DDRD	=$11
          .equ	PIND	=$10
         
         
         ;***** Bit Definitions
         
          .equ	INT0	=6
         
          .equ	TOIE0	=1
         
          .equ	TOV0	=1
         
          .equ	ISC01	=1
          .equ	ISC00	=0
         
          .equ	CS02	=2
          .equ	CS01	=1
          .equ	CS00	=0
         
          .def	ZP 	=r30
         
         
          .def 	key = r16
          .def	temp = r17
          .def	B = r18
          .def	C = r19
          .def	addsub = r24
          .def	counter = r25
          .def	tcount = r26
          .def	led = r27
         
          .cseg
000000 c015      	rjmp	reset
000001 c001      	rjmp	extint
000002 c005      	rjmp	timer
         
          extint:
000003 2722      	clr	B
000004 2733      	clr	C
000005 2788      	clr	addsub
000006 bb38      	out	portb,c
000007 9518      	reti
         
          timer:
000008 b71f      	in	temp,sreg
000009 95a3      	inc	tcount
00000a 31a8      	cpi	tcount,24
00000b f449      	brne	tback
00000c 27aa      	clr	tcount
00000d 31b0      	cpi	led,0b10000
00000e f409      	brne	t4
00000f e0b1      	ldi	led,0b0001	
000010 95b0      t4:	com	led
000011 bbb5      	out	portc,led
000012 95b0      	com	led
000013 0fbb      	lsl	led
000014 bf1f      	out	sreg,temp
000015 9518      tback:	reti			
         
         
          reset:
         
000016 2722      	clr	B
000017 2733      	clr	C
000018 2788      	clr	addsub
000019 e093      	ldi	counter,3
00001a e0b1      	ldi	led,0b0001
         
00001b ef10      	ldi	temp,0b11110000
00001c bb11      	out	ddrd,temp
00001d ef1f      	ser	temp
00001e bb17      	out	ddrb,temp	; PORT B as output
00001f bb14      	out	ddrc,temp	; PORT C as output
000020 bb15      	out	portc,temp	; PORT C leds OFF
000021 bb12      	out	portd,temp	; PORT D output HI
000022 bf1b      	out	gimsk,temp	; Enable external interrupt
000023 bf19      	out	timsk,temp	; Enable Timer interrupt
000024 e015      	ldi	temp,5
000025 bf13      	out	tccr0,temp	; timer clock source = divide by 1024
         
000026 d052      	rcall	ldtable
000027 9478      	sei
         
         ;*************************************************
         ; Detect Keys
         
000028 d04c      rescan: rcall	sdelay
         	
000029 9a96      	sbi	portd,6
00002a 9894      	cbi	portd,4
00002b e6e0      	ldi	zp,table
00002c b300      	in	key,pind
00002d 700f      	cbr	key,$F0
00002e 300f      	cpi	key,$0F
00002f f479      	brne	press
         
000030 9a94      	sbi	portd,4
000031 9895      	cbi	portd,5
000032 e6e1      	ldi	zp,table+1
000033 b300      	in	key,pind
000034 700f      	cbr	key,$F0
000035 300f      	cpi	key,$0F
000036 f441      	brne	press
         
000037 9a95      	sbi	portd,5
000038 9896      	cbi	portd,6
000039 e6e2      	ldi	zp,table+2
00003a b300      	in	key,pind
00003b 700f      	cbr	key,$F0
00003c 300f      	cpi	key,$0F
00003d f409      	brne	press
         
00003e cfe9      	rjmp	rescan
         
          press:
00003f d035      	rcall	sdelay
000040 b310      	in	temp,pind
000041 701f      	cbr	temp,$F0
000042 1301      	cpse	key,temp
000043 cfe4      	rjmp	rescan
000044 ff01      	sbrs	key,1
000045 5fed      	subi	zp,-3
000046 ff02      	sbrs	key,2
000047 5fea      	subi	zp,-6
000048 ff03      	sbrs	key,3	
000049 5fe7      	subi	zp,-9
00004a 8100      	ld	key,Z
         
         ;*************************************************
         ; Operation
         
00004b 300a      	cpi	key,$A
00004c f039      	breq	addkey
00004d 300b      	cpi	key,$B
00004e f039      	breq	subkey
         	
00004f 9522      	swap	B
000050 7f20      	cbr	B,$0f
000051 0f20      	add	B,key
000052 bb28      	out	portb,B
         
000053 c010      	rjmp	holding
         
          addkey:
000054 7f8e      	cbr	addsub,$01
000055 c001      	rjmp	arith
         
          subkey:
000056 6081      	sbr	addsub,$01
         
          arith:
000057 9582      	swap	addsub
000058 fd80      	sbrc	addsub,0
000059 c005      	rjmp	subf
00005a d046      	rcall	BCDadd
00005b bb38      	out	portb,C
00005c d00e      	rcall	overflow
00005d 2722      	clr	B
00005e c005      	rjmp	holding
         
          subf:
00005f d054      	rcall	BCDsub
000060 bb38      	out	portb,C
000061 d009      	rcall	overflow
000062 2722      	clr	B
000063 c000      	rjmp	holding
         
         ;*************************************************
         ; Key press released ?
         
          holding:
000064 d010      	rcall	sdelay
000065 b300      	in	key,pind
000066 700f      	cbr	key,$F0
000067 e01f      	ldi	temp,$0F
000068 1301      	cpse	key,temp
000069 cffa      	rjmp	holding
00006a cfbd      	rjmp	rescan
         
         ;*************************************************
         ; overflow ?
         
          overflow:
00006b ff20      	sbrs	b,0
00006c 9508      	ret
00006d 94f8      	cli
00006e 9a8f      	sbi	ddrd,7
00006f 9897      	cbi	portd,7
000070 d022      	rcall	delay
000071 9a97      	sbi	portd,7
000072 988f      	cbi	ddrd,7
000073 9478      	sei
000074 9508      	ret
         
         ;*************************************************
         ; Short Delay
         
          sdelay:
000075 2711      	clr	temp
000076 951a      s10:	dec	temp
000077 f7f1      	brne	s10
000078 9508      	ret
         
         ;*************************************************
         ; Load Table
         
          ldtable:
000079 e6e0      	ldi	ZP,table
00007a e011      	ldi	temp,1
00007b 9311      	st	Z+,temp
00007c e012      	ldi	temp,2
00007d 9311      	st	Z+,temp
00007e e013      	ldi	temp,3
00007f 9311      	st	Z+,temp
000080 e014      	ldi	temp,4
000081 9311      	st	Z+,temp
000082 e015      	ldi	temp,5
000083 9311      	st	Z+,temp
000084 e016      	ldi	temp,6
000085 9311      	st	Z+,temp
000086 e017      	ldi	temp,7
000087 9311      	st	Z+,temp
000088 e018      	ldi	temp,8
000089 9311      	st	Z+,temp
00008a e019      	ldi	temp,9
00008b 9311      	st	Z+,temp
00008c e01b      	ldi	temp,$B
00008d 9311      	st	Z+,temp
00008e e010      	ldi	temp,0
00008f 9311      	st	Z+,temp
000090 e01a      	ldi	temp,$A
000091 9311      	st	Z+,temp
000092 9508      	ret
         
         ;*******************************************	
          delay:
000093 e6ec      del:	ldi	ZP,count
000094 8110      	ld	temp,Z
000095 951a      	dec	temp
000096 8310      	st	Z,temp
000097 f7d9      	brne	del
000098 e6ed      	ldi	ZP,count+1
000099 8110      	ld	temp,Z
00009a 951a      	dec	temp
00009b 8310      	st	Z,temp
00009c f7b1      	brne	del
00009d 959a      	dec	counter
00009e f7a1      	brne	del
00009f e093      	ldi	counter,3
0000a0 9508      	ret
         
         ;***** Subroutine Register Variables
         
          .def	BCD1	=r19		;BCD input value #1
          .def	BCD2	=r18		;BCD input value #2
          .def	tmpadd	=r16		;temporary register
         
         ;***** Code
         
          BCDadd:
0000a1 e006      	ldi	tmpadd,6	;value to be added later
0000a2 0f32      	add	BCD1,BCD2	;add the numbers binary
0000a3 2722      	clr	BCD2		;clear BCD carry
0000a4 f408      	brcc	add_0		;if carry not clear
0000a5 e021      	ldi	BCD2,1		;    set BCD carry
0000a6 f025      add_0:	brhs	add_1		;if half carry not set
0000a7 0f30      	add	BCD1,tmpadd	;    add 6 to LSD
0000a8 f01d      	brhs	add_2		;    if half carry not set (LSD <= 9)
0000a9 5036      	subi	BCD1,6		;        restore value
0000aa c001      	rjmp	add_2		;else
0000ab 0f30      add_1:	add	BCD1,tmpadd	;    add 6 to LSD
0000ac 9502      add_2:	swap	tmpadd
0000ad 0f30      	add	BCD1,tmpadd	;add 6 to MSD
0000ae f018      	brcs	add_4		;if carry not set (MSD <= 9)
0000af ff20      	sbrs	BCD2,0		;    if previous carry not set
0000b0 5630      	subi	BCD1,$60	;	restore value 
0000b1 9508      add_3:	ret			;else
0000b2 e021      add_4:	ldi	BCD2,1		;    set BCD carry
0000b3 9508      	ret
         
         
         ;***** Subroutine Register Variables
         
          .def	BCDa	=r19		;BCD input value #1
          .def	BCDb	=r18		;BCD input value #2
         
         ;***** Code
         
          BCDsub:
0000b4 1b32      	sub	BCDa,BCDb	;subtract the numbers binary
0000b5 2722      	clr	BCDb
0000b6 f408      	brcc	sub_0		;if carry not clear
0000b7 e021      	ldi	BCDb,1		;    store carry in BCDB1, bit 0
0000b8 f40d      sub_0:	brhc	sub_1		;if half carry not clear
0000b9 5036      	subi	BCDa,$06	;    LSD = LSD - 6
0000ba ff20      sub_1:	sbrs	BCDb,0		;if previous carry not set
0000bb 9508      	ret			;    return
0000bc 5630      	subi	BCDa,$60	;subtract 6 from MSD
0000bd e021      	ldi	BCDb,1		;set underflow carry
0000be f408      	brcc	sub_2		;if carry not clear
0000bf e021      	ldi	BCDb,1		;    clear underflow carry	
0000c0 9508      sub_2:	ret			
         
         
         
         	
          .dseg
000060      table:	.byte	12
00006c      count:	.byte	2
Assembly complete with no errors.
@


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