head 1.1; branch 1.1.1; access ; symbols arelease:1.1.1.1 avendor:1.1.1; locks ; strict; comment @# @; 1.1 date 2008.04.08.20.00.35; author fpga_is_funny; state Exp; branches 1.1.1.1; next ; commitid 2b3f47fbcb9e4567; 1.1.1.1 date 2008.04.08.20.00.35; author fpga_is_funny; state Exp; branches ; next ; commitid 2b3f47fbcb9e4567; desc @@ 1.1 log @Initial revision @ text @ R6502_TC\R6502_TC\symbol_sb

Declarations

Ports:

clk_clk_i   : in     std_logic  ;
d_i         : in     std_logic_vector (7 DOWNTO 0) ;
irq_n_i     : in     std_logic  ;
nmi_n_i     : in     std_logic  ;
rdy_i       : in     std_logic  ;
rst_rst_n_i : in     std_logic  ;
so_n_i      : in     std_logic  ;
a_o         : out    std_logic_vector (15 DOWNTO 0) ;
d_o         : out    std_logic_vector (7 DOWNTO 0) ;
rd_o        : out    std_logic  ;
sync_o      : out    std_logic  ;
wr_n_o      : out    std_logic  ;
wr_o        : out    std_logic

User:



Generic Declarations


Package List


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;










@


1.1.1.1
log
@First Revision
After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile
The CVS history in the VHDL files is fine now.
@
text
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