head	1.1;
branch	1.1.1;
access;
symbols
	add:1.1.1.1
	update:1.1.1.2
	samiam95124:1.1.1;
locks; strict;
comment	@# @;


1.1
date	2006.11.01.19.56.17;	author samiam95124;	state Exp;
branches
	1.1.1.1;
next	;
commitid	31604548faf04567;

1.1.1.1
date	2006.11.01.19.56.17;	author samiam95124;	state Exp;
branches;
next	1.1.1.2;
commitid	31604548faf04567;

1.1.1.2
date	2006.11.11.11.58.47;	author samiam95124;	state Exp;
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next	;
commitid	1fa44555b9f14567;


desc
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1.1
log
@Initial revision
@
text
@vhdl work "common.vhd"
vhdl work "vga.vhd"
verilog work "vgachr.v"
verilog work "cpu8080.v"
verilog work "testbench.v"
verilog work C:/Xilinx/verilog/src/glbl.v
@


1.1.1.1
log
@8080 CPU project
@
text
@@


1.1.1.2
log
@8080 CPU project
@
text
@a3 1
vhdl work "ps2_kbd.vhd"
@