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desc
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1.1
log
@Initial revision
@
text
@Release 8.2.02i - xst I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.23 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.23 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: testbench.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "testbench.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "testbench"
Output Format                      : NGC
Target Device                      : xc3s200-5-pq208

---- Source Options
Top Module Name                    : testbench
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : testbench.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "cpu8080.v" in library work
Module <cpu8080> compiled
Compiling verilog file "testbench.v" in library work
Module <alu> compiled
Module <testbench> compiled
Module <select> compiled
Module <selectone> compiled
Module <rom> compiled
Module <ram> compiled
No errors in compilation
Analysis of file <"testbench.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <testbench> in library <work>.

Analyzing hierarchy for module <select> in library <work>.

Analyzing hierarchy for module <cpu8080> in library <work>.

Analyzing hierarchy for module <rom> in library <work>.

Analyzing hierarchy for module <ram> in library <work>.

Analyzing hierarchy for module <selectone> in library <work>.

Analyzing hierarchy for module <alu> in library <work>.

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <testbench>.
Module <testbench> is correct for synthesis.
 
Analyzing module <select> in library <work>.
Module <select> is correct for synthesis.
 
Analyzing module <selectone> in library <work>.
WARNING:Xst:905 - "testbench.v" line 229: The signals <reset, selectin, data, comp, mask> are missing in the sensitivity list of always block.
Module <selectone> is correct for synthesis.
 
Analyzing module <cpu8080> in library <work>.
Module <cpu8080> is correct for synthesis.
 
Analyzing module <alu> in library <work>.
Module <alu> is correct for synthesis.
 
Analyzing module <rom> in library <work>.
Module <rom> is correct for synthesis.
 
Analyzing module <ram> in library <work>.
Module <ram> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <rom>.
    Related source file is "testbench.v".
    Found 8-bit tristate buffer for signal <data>.
    Summary:
	inferred   8 Tristate(s).
Unit <rom> synthesized.


Synthesizing Unit <ram>.
    Related source file is "testbench.v".
    Found 1024x8-bit single-port block RAM for signal <ramcore>.
    -----------------------------------------------------------------------
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1024-word x 8-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clock>         | rise     |
    |     enA            | connected to signal <select>        | high     |
    |     weA            | connected to signal <write>         | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <data>          |          |
    |     doA            | connected to signal <datao>         |          |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <data>.
    Summary:
	inferred   1 RAM(s).
	inferred   8 Tristate(s).
Unit <ram> synthesized.


Synthesizing Unit <selectone>.
    Related source file is "testbench.v".
WARNING:Xst:647 - Input <addr<9:8>> is never used.
WARNING:Xst:647 - Input <addr<1>> is never used.
WARNING:Xst:737 - Found 6-bit latch for signal <comp>.
WARNING:Xst:737 - Found 8-bit latch for signal <mask>.
WARNING:Xst:737 - Found 8-bit latch for signal <datai>.
    Found 8-bit tristate buffer for signal <data>.
    Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 226.
    Summary:
	inferred   1 Comparator(s).
	inferred   8 Tristate(s).
Unit <selectone> synthesized.


Synthesizing Unit <alu>.
    Related source file is "cpu8080.v".
WARNING:Xst:646 - Signal <resi> is assigned but never used.
    Found 1-bit 8-to-1 multiplexer for signal <cout>.
    Found 1-bit 8-to-1 multiplexer for signal <auxcar>.
    Found 5-bit adder for signal <$add0001> created at line 1441.
    Found 8-bit adder carry out for signal <$addsub0000> created at line 1434.
    Found 4-bit adder carry out for signal <$addsub0001> created at line 1435.
    Found 6-bit subtractor for signal <$sub0000> created at line 1447.
    Found 6-bit subtractor for signal <$sub0001> created at line 1453.
    Found 9-bit subtractor for signal <$sub0002> created at line 1446.
    Found 8-bit xor2 for signal <$xor0000> created at line 1464.
    Found 1-bit xor8 for signal <$xor0002>.
    Summary:
	inferred   8 Adder/Subtractor(s).
	inferred  10 Multiplexer(s).
	inferred   1 Xor(s).
Unit <alu> synthesized.


Synthesizing Unit <select>.
    Related source file is "testbench.v".
    Found 1-bit register for signal <bootstrap>.
    Found 8-bit tristate buffer for signal <data>.
    Found 8-bit register for signal <datai>.
    Found 4-bit comparator equal for signal <selacc>.
    Found 4-bit register for signal <seladr>.
    Summary:
	inferred  13 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   8 Tristate(s).
Unit <select> synthesized.


Synthesizing Unit <cpu8080>.
    Related source file is "cpu8080.v".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 30                                             |
    | Transitions        | 897                                            |
    | Inputs             | 138                                            |
    | Outputs            | 31                                             |
    | Clock              | clock (rising_edge)                            |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 00001                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4x1-bit ROM for signal <$mux0041> created at line 271.
    Found 16-bit register for signal <addr>.
    Found 1-bit register for signal <writeio>.
    Found 1-bit register for signal <readio>.
    Found 1-bit register for signal <writemem>.
    Found 1-bit register for signal <readmem>.
    Found 1-bit register for signal <inta>.
    Found 8-bit tristate buffer for signal <data>.
    Found 32-bit adder for signal <$add0001> created at line 453.
    Found 32-bit adder for signal <$add0002> created at line 465.
    Found 32-bit adder for signal <$add0003> created at line 477.
    Found 16-bit adder for signal <$add0004> created at line 930.
    Found 16-bit adder for signal <$add0005> created at line 845.
    Found 32-bit adder for signal <$add0006> created at line 522.
    Found 32-bit adder for signal <$add0007> created at line 510.
    Found 32-bit adder for signal <$add0008> created at line 498.
    Found 17-bit adder for signal <$add0009> created at line 443.
    Found 17-bit adder for signal <$addsub0000>.
    Found 17-bit adder for signal <$addsub0001>.
    Found 17-bit adder for signal <$addsub0002>.
    Found 8-bit adder for signal <$addsub0003>.
    Found 8-bit addsub for signal <$addsub0004>.
    Found 8-bit addsub for signal <$addsub0005>.
    Found 8-bit addsub for signal <$addsub0006>.
    Found 16-bit adder for signal <$addsub0007> created at line 1001.
    Found 16-bit adder for signal <$addsub0008> created at line 1042.
    Found 8-bit adder carry out for signal <$addsub0009>.
    Found 4-bit adder carry out for signal <$addsub0010> created at line 318.
    Found 8-bit adder carry out for signal <$addsub0011>.
    Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 315.
    Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1251.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0020> created at line 271.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0021> created at line 271.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0023> created at line 271.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0029> created at line 271.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0043>.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0048> created at line 275.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0049>.
    Found 16-bit adder for signal <$share0000> created at line 271.
    Found 6-bit adder for signal <$share0005> created at line 250.
    Found 16-bit addsub for signal <$share0006> created at line 271.
    Found 32-bit subtractor for signal <$sub0000> created at line 498.
    Found 32-bit subtractor for signal <$sub0001> created at line 510.
    Found 32-bit subtractor for signal <$sub0002> created at line 522.
    Found 16-bit subtractor for signal <$sub0003> created at line 719.
    Found 1-bit register for signal <alucin>.
    Found 8-bit register for signal <aluopra>.
    Found 8-bit register for signal <aluoprb>.
    Found 3-bit register for signal <alusel>.
    Found 1-bit register for signal <auxcar>.
    Found 1-bit register for signal <carry>.
    Found 1-bit register for signal <dataeno>.
    Found 8-bit register for signal <datao>.
    Found 1-bit register for signal <ei>.
    Found 1-bit register for signal <parity>.
    Found 16-bit register for signal <pc>.
    Found 2-bit register for signal <popdes>.
    Found 16-bit register for signal <raddrhold>.
    Found 8-bit register for signal <rdatahold>.
    Found 8-bit register for signal <rdatahold2>.
    Found 3-bit register for signal <regd>.
    Found 64-bit register for signal <regfil>.
    Found 1-bit register for signal <sign>.
    Found 16-bit register for signal <sp>.
    Found 6-bit register for signal <statesel>.
    Found 16-bit register for signal <waddrhold>.
    Found 8-bit register for signal <wdatahold>.
    Found 8-bit register for signal <wdatahold2>.
    Found 1-bit register for signal <zero>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred 227 D-type flip-flop(s).
	inferred  34 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred  52 Multiplexer(s).
	inferred   8 Tristate(s).
Unit <cpu8080> synthesized.


Synthesizing Unit <testbench>.
    Related source file is "testbench.v".
WARNING:Xst:646 - Signal <select2> is assigned but never used.
WARNING:Xst:646 - Signal <select4> is assigned but never used.
WARNING:Xst:646 - Signal <bootstrap> is assigned but never used.
    Found 8-bit tristate buffer for signal <data>.
    Summary:
	inferred   8 Tristate(s).
Unit <testbench> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 1024x8-bit single-port block RAM                      : 1
# ROMs                                                 : 1
 4x1-bit ROM                                           : 1
# Adders/Subtractors                                   : 42
 16-bit adder                                          : 5
 16-bit addsub                                         : 1
 16-bit subtractor                                     : 1
 17-bit adder                                          : 8
 32-bit adder                                          : 6
 32-bit subtractor                                     : 3
 4-bit adder carry out                                 : 2
 5-bit adder                                           : 1
 6-bit adder                                           : 1
 6-bit subtractor                                      : 2
 8-bit adder                                           : 1
 8-bit adder carry out                                 : 3
 8-bit addsub                                          : 3
 9-bit adder                                           : 3
 9-bit subtractor                                      : 2
# Registers                                            : 40
 1-bit register                                        : 14
 16-bit register                                       : 5
 2-bit register                                        : 1
 3-bit register                                        : 2
 4-bit register                                        : 1
 6-bit register                                        : 1
 8-bit register                                        : 16
# Latches                                              : 12
 6-bit latch                                           : 4
 8-bit latch                                           : 8
# Comparators                                          : 7
 4-bit comparator equal                                : 1
 4-bit comparator greater                              : 2
 6-bit comparator equal                                : 4
# Multiplexers                                         : 12
 1-bit 8-to-1 multiplexer                              : 2
 3-bit 4-to-1 multiplexer                              : 4
 8-bit 4-to-1 multiplexer                              : 3
 8-bit 8-to-1 multiplexer                              : 3
# Tristates                                            : 9
 8-bit tristate buffer                                 : 9
# Xors                                                 : 2
 1-bit xor8                                            : 1
 8-bit xor2                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <cpu/state> on signal <state[1:32]> with speed1 encoding.
-------------------------------------------
 State | Encoding
-------------------------------------------
 00001 | 10000000000000000000000000000000
 00010 | 01000000000000000000000000000000
 00011 | 00000010000000000000000000000000
 00100 | 00000001000010000000000000000000
 00101 | 00010000000010000000000000000000
 00110 | 00000000000011000000000000000000
 00111 | 00000000000010100000000000000000
 01000 | 00000000000010010000000000000000
 01001 | 00000000000010001000000000000000
 01010 | 00000000000000000000000010000001
 01011 | 00000000000010000000010000000000
 01100 | 00001000000000000000000000000000
 01101 | 00000000100000000000000000000000
 01110 | 00000000010000000000000000000000
 01111 | 00000000001000000000000000000001
 10000 | 00000100000000000000000000000000
 10001 | 00000000000000000000000000100000
 10010 | 00000000000000000100000000000000
 10011 | 00000000000000000000000100000000
 10100 | 00000000000010000000000000010000
 10101 | 00000000000000000000000001000000
 10110 | 00000000000000000000000000001000
 10111 | 00000000000000000000000000000100
 11000 | 00000000000010000000000000000010
 11001 | 00000000000100000000000000000001
 11010 | 00000000000000000010000000000001
 11011 | 00000000000000000000100000000001
 11100 | 00000000000000000000001000000001
 11101 | 00000000000000000001000000000000
 11110 | 00100000000010000000000000000000
-------------------------------------------
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.
WARNING:Xst:1710 - FF/Latch  <datai_0> (without init value) has a constant value of 0 in block <select>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datai_1> (without init value) has a constant value of 0 in block <select>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datai_2> (without init value) has a constant value of 0 in block <select>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datai_3> (without init value) has a constant value of 0 in block <select>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# RAMs                                                 : 1
 1024x8-bit single-port block RAM                      : 1
# ROMs                                                 : 1
 4x1-bit ROM                                           : 1
# Adders/Subtractors                                   : 42
 16-bit adder                                          : 5
 16-bit addsub                                         : 1
 16-bit subtractor                                     : 1
 17-bit adder                                          : 8
 32-bit adder                                          : 6
 32-bit subtractor                                     : 3
 4-bit adder carry out                                 : 2
 5-bit adder                                           : 1
 6-bit adder                                           : 1
 6-bit subtractor                                      : 2
 8-bit adder                                           : 1
 8-bit adder carry out                                 : 3
 8-bit addsub                                          : 3
 9-bit adder                                           : 3
 9-bit subtractor                                      : 2
# Registers                                            : 267
 Flip-Flops                                            : 267
# Latches                                              : 12
 6-bit latch                                           : 4
 8-bit latch                                           : 8
# Comparators                                          : 7
 4-bit comparator equal                                : 1
 4-bit comparator greater                              : 2
 6-bit comparator equal                                : 4
# Multiplexers                                         : 12
 1-bit 8-to-1 multiplexer                              : 2
 3-bit 4-to-1 multiplexer                              : 4
 8-bit 4-to-1 multiplexer                              : 3
 8-bit 8-to-1 multiplexer                              : 3
# Xors                                                 : 2
 1-bit xor8                                            : 1
 8-bit xor2                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2040 - Unit testbench: 8 multi-source signals are replaced by logic (pull-up yes): N11, N13, N15, N17, N3, N5, N7, N9.

Optimizing unit <testbench> ...

Optimizing unit <alu> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 65.
FlipFlop cpu/alusel_0 has been replicated 2 time(s)
FlipFlop cpu/alusel_1 has been replicated 2 time(s)
FlipFlop cpu/alusel_2 has been replicated 2 time(s)
FlipFlop cpu/regd_0 has been replicated 1 time(s)
FlipFlop cpu/regd_1 has been replicated 1 time(s)
FlipFlop cpu/regd_2 has been replicated 1 time(s)
FlipFlop cpu/regfil_5_0 has been replicated 1 time(s)
FlipFlop cpu/regfil_5_1 has been replicated 2 time(s)
FlipFlop cpu/state_FFd12 has been replicated 3 time(s)
FlipFlop cpu/state_FFd18 has been replicated 2 time(s)
FlipFlop cpu/state_FFd2 has been replicated 4 time(s)
FlipFlop cpu/state_FFd4 has been replicated 3 time(s)
FlipFlop cpu/statesel_1 has been replicated 1 time(s)
FlipFlop cpu/statesel_2 has been replicated 2 time(s)
FlipFlop cpu/statesel_3 has been replicated 2 time(s)
FlipFlop cpu/statesel_4 has been replicated 1 time(s)
FlipFlop cpu/statesel_5 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 297
 Flip-Flops                                            : 297

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : testbench.ngr
Top Level Output File Name         : testbench
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 33

Cell Usage :
# BELS                             : 2939
#      GND                         : 1
#      INV                         : 82
#      LUT1                        : 139
#      LUT2                        : 154
#      LUT2_D                      : 6
#      LUT2_L                      : 3
#      LUT3                        : 306
#      LUT3_D                      : 20
#      LUT3_L                      : 32
#      LUT4                        : 1115
#      LUT4_D                      : 41
#      LUT4_L                      : 255
#      MULT_AND                    : 28
#      MUXCY                       : 279
#      MUXF5                       : 215
#      MUXF6                       : 24
#      VCC                         : 1
#      XORCY                       : 238
# FlipFlops/Latches                : 371
#      FDE                         : 226
#      FDR                         : 27
#      FDRE                        : 5
#      FDRS                        : 34
#      FDRSE                       : 2
#      FDS                         : 1
#      FDSE                        : 2
#      LDCE                        : 50
#      LDE_1                       : 24
# RAMS                             : 1
#      RAMB16_S9                   : 1
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 31
#      IBUF                        : 2
#      IOBUF                       : 8
#      OBUF                        : 21
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-5 

 Number of Slices:                    1139  out of   1920    59%  
 Number of Slice Flip Flops:           371  out of   3840     9%  
 Number of 4 input LUTs:              2153  out of   3840    56%  
 Number of IOs:                         33
 Number of bonded IOBs:                 33  out of    141    23%  
 Number of BRAMs:                        1  out of     12     8%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------------------------+--------------------------------+-------+
Clock Signal                                         | Clock buffer(FF name)          | Load  |
-----------------------------------------------------+--------------------------------+-------+
clock                                                | BUFGP                          | 297   |
reset                                                | BUFGP                          | 24    |
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_7)| 11    |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_1)| 11    |
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/mask_2)| 14    |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/comp_3)| 14    |
-----------------------------------------------------+--------------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
reset                              | BUFGP                  | 50    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.734ns (Maximum Frequency: 102.728MHz)
   Minimum input arrival time before clock: 15.385ns
   Maximum output required time after clock: 16.387ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clock'
  Clock period: 9.734ns (frequency: 102.728MHz)
  Total number of paths / destination ports: 22856 / 378
-------------------------------------------------------------------------
Delay:               9.734ns (Levels of Logic = 10)
  Source:            cpu/aluoprb_0 (FF)
  Destination:       cpu/regfil_2_5 (FF)
  Source Clock:      clock rising
  Destination Clock: clock rising

  Data Path: cpu/aluoprb_0 to cpu/regfil_2_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             13   0.626   1.289  cpu/aluoprb_0 (cpu/aluoprb_0)
     LUT2:I0->O            1   0.479   0.000  cpu/alu/Msub__sub0002_lut<0> (cpu/alu/N19)
     MUXCY:S->O            1   0.435   0.000  cpu/alu/Msub__sub0002_cy<0> (cpu/alu/Msub__sub0002_cy<0>)
     MUXCY:CI->O           1   0.056   0.000  cpu/alu/Msub__sub0002_cy<1> (cpu/alu/Msub__sub0002_cy<1>)
     MUXCY:CI->O           1   0.056   0.000  cpu/alu/Msub__sub0002_cy<2> (cpu/alu/Msub__sub0002_cy<2>)
     XORCY:CI->O           7   0.786   1.076  cpu/alu/Msub__sub0002_xor<3> (cpu/alu/_sub0002<3>)
     LUT2:I1->O            1   0.479   0.740  cpu/alu/Msub__AUX_32_xor<5>11_SW0 (N9996)
     LUT4:I2->O            1   0.479   0.000  cpu/alu/sel<0>22 (cpu/alu/N241)
     MUXF5:I1->O           2   0.314   0.745  cpu/alu/sel<1>_f5_10 (cpu/alu/sel<1>_f511)
     MUXF5:S->O            8   0.540   0.980  cpu/alu/res<5>1 (cpu/alures<5>)
     LUT4:I2->O            1   0.479   0.000  cpu/_mux0016<5>60 (cpu/_mux0016<5>)
     FDE:D                     0.176          cpu/regfil_2_5
    ----------------------------------------
    Total                      9.734ns (4.904ns logic, 4.830ns route)
                                       (50.4% logic, 49.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
  Total number of paths / destination ports: 15524 / 569
-------------------------------------------------------------------------
Offset:              15.385ns (Levels of Logic = 10)
  Source:            data<4> (PAD)
  Destination:       cpu/regfil_1_5 (FF)
  Destination Clock: clock rising

  Data Path: data<4> to cpu/regfil_1_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O         153   0.715   2.459  data_4_IOBUF (N9902)
     LUT2:I0->O           18   0.479   1.227  cpu/_mux0026<5>29 (N112)
     LUT4:I3->O           14   0.479   1.304  cpu/_cmp_eq00652 (cpu/_cmp_eq0065)
     LUT4:I0->O            1   0.479   0.976  cpu/_cmp_eq00671_SW0 (N10381)
     LUT4_D:I0->O         10   0.479   0.987  cpu/_mux0016<7>1113 (N149)
     LUT4:I3->O            1   0.479   0.740  cpu/_mux0015<2>31_SW2 (N10542)
     LUT4:I2->O            8   0.479   0.944  cpu/_mux0015<2>31 (N277)
     LUT4:I3->O            2   0.479   0.745  cpu/_mux0015<5>38 (cpu/_mux0015<5>_map1354)
     MUXF5:S->O            1   0.540   0.740  cpu/_mux0012<5>31_SW5 (N10424)
     LUT4:I2->O            1   0.479   0.000  cpu/_mux0015<5>40 (cpu/_mux0015<5>)
     FDE:D                     0.176          cpu/regfil_1_5
    ----------------------------------------
    Total                     15.385ns (5.263ns logic, 10.122ns route)
                                       (34.2% logic, 65.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              3.304ns (Levels of Logic = 1)
  Source:            data<3> (PAD)
  Destination:       select1/selectd/mask_3 (LATCH)
  Destination Clock: select1/selectd/_and0000 falling

  Data Path: data<3> to select1/selectd/mask_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O         204   0.715   2.413  data_3_IOBUF (N9903)
     LDCE:D                    0.176          select1/selectd/mask_3
    ----------------------------------------
    Total                      3.304ns (0.891ns logic, 2.413ns route)
                                       (27.0% logic, 73.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              3.304ns (Levels of Logic = 1)
  Source:            data<3> (PAD)
  Destination:       select1/selectc/mask_3 (LATCH)
  Destination Clock: select1/selectc/_and0000 falling

  Data Path: data<3> to select1/selectc/mask_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O         204   0.715   2.413  data_3_IOBUF (N9903)
     LDCE:D                    0.176          select1/selectc/mask_3
    ----------------------------------------
    Total                      3.304ns (0.891ns logic, 2.413ns route)
                                       (27.0% logic, 73.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              3.304ns (Levels of Logic = 1)
  Source:            data<3> (PAD)
  Destination:       select1/selectb/mask_3 (LATCH)
  Destination Clock: select1/selectb/_and0000 falling

  Data Path: data<3> to select1/selectb/mask_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O         204   0.715   2.413  data_3_IOBUF (N9903)
     LDCE:D                    0.176          select1/selectb/mask_3
    ----------------------------------------
    Total                      3.304ns (0.891ns logic, 2.413ns route)
                                       (27.0% logic, 73.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              3.304ns (Levels of Logic = 1)
  Source:            data<3> (PAD)
  Destination:       select1/selecta/mask_3 (LATCH)
  Destination Clock: select1/selecta/_and0000 falling

  Data Path: data<3> to select1/selecta/mask_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O         204   0.715   2.413  data_3_IOBUF (N9903)
     LDCE:D                    0.176          select1/selecta/mask_3
    ----------------------------------------
    Total                      3.304ns (0.891ns logic, 2.413ns route)
                                       (27.0% logic, 73.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  Total number of paths / destination ports: 1369 / 29
-------------------------------------------------------------------------
Offset:              16.387ns (Levels of Logic = 9)
  Source:            cpu/addr_2 (FF)
  Destination:       data<7> (PAD)
  Source Clock:      clock rising

  Data Path: cpu/addr_2 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             31   0.626   1.593  cpu/addr_2 (cpu/addr_2)
     LUT4:I3->O            1   0.479   0.000  select1/select11021 (N11407)
     MUXF5:I1->O           1   0.314   0.851  select1/select1102_f5 (select1/select1_map3479)
     LUT4:I1->O            1   0.479   0.851  select1/select1123 (select1/select1_map3481)
     LUT4:I1->O           10   0.479   1.259  select1/select1446 (romsel)
     LUT3:I0->O            2   0.479   1.040  N11LogicTrst438 (N565)
     LUT4:I0->O            4   0.479   1.074  N17LogicTrst21 (N191)
     LUT4:I0->O            1   0.479   0.000  N17LogicTrst802 (N11410)
     MUXF5:I0->O           1   0.314   0.681  N17LogicTrst80_f5 (data_0_IOBUF)
     IOBUF:I->IO               4.909          data_0_IOBUF (data<0>)
    ----------------------------------------
    Total                     16.387ns (9.037ns logic, 7.350ns route)
                                       (55.1% logic, 44.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
  Total number of paths / destination ports: 810 / 8
-------------------------------------------------------------------------
Offset:              15.933ns (Levels of Logic = 9)
  Source:            select1/selecta/mask_1 (LATCH)
  Destination:       data<7> (PAD)
  Source Clock:      select1/selecta/_and0000 falling

  Data Path: select1/selecta/mask_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             7   0.551   1.201  select1/selecta/mask_1 (select1/selecta/mask_1)
     LUT4:I0->O            1   0.479   0.000  select1/select11961 (N11471)
     MUXF5:I1->O           1   0.314   0.976  select1/select1196_f5 (select1/select1_map3499)
     LUT4:I0->O            1   0.479   0.740  select1/select1420 (select1/select1_map3553)
     LUT4:I2->O           10   0.479   1.259  select1/select1446 (romsel)
     LUT3:I0->O            2   0.479   1.040  N11LogicTrst438 (N565)
     LUT4:I0->O            4   0.479   1.074  N17LogicTrst21 (N191)
     LUT4:I0->O            1   0.479   0.000  N17LogicTrst802 (N11410)
     MUXF5:I0->O           1   0.314   0.681  N17LogicTrst80_f5 (data_0_IOBUF)
     IOBUF:I->IO               4.909          data_0_IOBUF (data<0>)
    ----------------------------------------
    Total                     15.933ns (8.962ns logic, 6.971ns route)
                                       (56.2% logic, 43.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'
  Total number of paths / destination ports: 806 / 8
-------------------------------------------------------------------------
Offset:              16.154ns (Levels of Logic = 10)
  Source:            select1/selectb/mask_1 (LATCH)
  Destination:       data<7> (PAD)
  Source Clock:      select1/selectb/_and0000 falling

  Data Path: select1/selectb/mask_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             7   0.551   1.201  select1/selectb/mask_1 (select1/selectb/mask_1)
     LUT4:I0->O            1   0.479   0.000  select1/selectb/_cmp_eq000011 (N11441)
     MUXF5:I1->O           3   0.314   1.066  select1/selectb/_cmp_eq00001_f5 (select1/selectb/_cmp_eq00002)
     LUT3:I0->O            1   0.479   0.000  ram/_and0000_inv231 (N11451)
     MUXF5:I1->O           1   0.314   0.740  ram/_and0000_inv23_f5 (ram/_and0000_inv_map3882)
     LUT4:I2->O           12   0.479   1.120  ram/_and0000_inv79 (ram/_and0000_inv)
     LUT4:I1->O           11   0.479   0.995  N21 (N2)
     LUT4:I3->O            4   0.479   1.074  N17LogicTrst21 (N191)
     LUT4:I0->O            1   0.479   0.000  N17LogicTrst802 (N11410)
     MUXF5:I0->O           1   0.314   0.681  N17LogicTrst80_f5 (data_0_IOBUF)
     IOBUF:I->IO               4.909          data_0_IOBUF (data<0>)
    ----------------------------------------
    Total                     16.154ns (9.276ns logic, 6.878ns route)
                                       (57.4% logic, 42.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset'
  Total number of paths / destination ports: 41 / 6
-------------------------------------------------------------------------
Offset:              11.595ns (Levels of Logic = 6)
  Source:            select1/selecta/datai_3 (LATCH)
  Destination:       data<3> (PAD)
  Source Clock:      reset rising

  Data Path: select1/selecta/datai_3 to data<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE_1:G->Q            2   0.551   0.804  select1/selecta/datai_3 (select1/selecta/datai_3)
     LUT4:I2->O            1   0.479   0.000  N11LogicTrst461_SW02 (N11480)
     MUXF5:I0->O           1   0.314   0.740  N11LogicTrst461_SW0_f5 (N11197)
     LUT4:I2->O            1   0.479   0.976  N11LogicTrst461 (N11LogicTrst_map3597)
     LUT4:I0->O            1   0.479   0.704  N11LogicTrst76 (N11LogicTrst_map3602)
     LUT4:I3->O            1   0.479   0.681  N11LogicTrst87 (data_3_IOBUF)
     IOBUF:I->IO               4.909          data_3_IOBUF (data<3>)
    ----------------------------------------
    Total                     11.595ns (7.690ns logic, 3.905ns route)
                                       (66.3% logic, 33.7% route)

=========================================================================
CPU : 119.56 / 119.83 s | Elapsed : 119.00 / 120.00 s
 
--> 

Total memory usage is 198928 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   15 (   0 filtered)
Number of infos    :    2 (   0 filtered)

@


1.1.1.1
log
@8080 CPU project
@
text
@@


1.1.1.2
log
@8080 CPU project
@
text
@d4 1
a4 1
CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s
d7 1
a7 1
CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s
a105 2
Module <intcontrol> compiled
Compiling verilog include file "test.lst"
a124 2
Analyzing hierarchy for module <intcontrol> in library <work>.

d141 1
a155 3
Analyzing module <intcontrol> in library <work>.
Module <intcontrol> is correct for synthesis.
 
a161 1
INFO:Xst:1304 - Contents of register <eienb> in unit <cpu8080> never changes during circuit operation. The register is replaced by logic.
a164 1
    Found 512x8-bit ROM for signal <$mux0000>.
a166 1
	inferred   1 ROM(s).
d180 1
a180 1
    |     clkA           | connected to signal <clock>         | fall     |
a193 39
Synthesizing Unit <intcontrol>.
    Related source file is "testbench.v".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 3                                              |
    | Inputs             | 0                                              |
    | Outputs            | 4                                              |
    | Clock              | clock (falling_edge)                           |
    | Clock enable       | $not0004 (positive)                            |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <data>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0000>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0001>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0002>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0003>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0004>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0007>.
    Found 8-bit register for signal <active>.
    Found 8-bit register for signal <datai>.
    Found 8-bit register for signal <edges>.
    Found 8-bit register for signal <mask>.
    Found 8-bit register for signal <polarity>.
    Found 8-bit register for signal <vbase>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  48 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   8 Tristate(s).
Unit <intcontrol> synthesized.


d202 1
a202 1
    Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 264.
d214 7
a220 7
    Found 5-bit adder for signal <$add0001> created at line 1476.
    Found 8-bit adder carry out for signal <$addsub0000> created at line 1469.
    Found 4-bit adder carry out for signal <$addsub0001> created at line 1470.
    Found 6-bit subtractor for signal <$sub0000> created at line 1482.
    Found 6-bit subtractor for signal <$sub0001> created at line 1488.
    Found 9-bit subtractor for signal <$sub0002> created at line 1481.
    Found 8-bit xor2 for signal <$xor0000> created at line 1499.
d245 1
a245 1
    Found finite state machine <FSM_1> for signal <state>.
d248 2
a249 2
    | Transitions        | 899                                            |
    | Inputs             | 140                                            |
d258 1
a258 1
    Found 4x1-bit ROM for signal <$mux0042> created at line 293.
d266 9
a274 9
    Found 32-bit adder for signal <$add0001> created at line 475.
    Found 32-bit adder for signal <$add0002> created at line 487.
    Found 32-bit adder for signal <$add0003> created at line 499.
    Found 16-bit adder for signal <$add0004> created at line 959.
    Found 16-bit adder for signal <$add0005> created at line 870.
    Found 32-bit adder for signal <$add0006> created at line 544.
    Found 32-bit adder for signal <$add0007> created at line 532.
    Found 32-bit adder for signal <$add0008> created at line 520.
    Found 17-bit adder for signal <$add0009> created at line 465.
d282 2
a283 2
    Found 16-bit adder for signal <$addsub0007> created at line 1030.
    Found 16-bit adder for signal <$addsub0008> created at line 1071.
d285 1
a285 1
    Found 4-bit adder carry out for signal <$addsub0010> created at line 340.
d287 16
a302 16
    Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 337.
    Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1286.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0021> created at line 293.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0022> created at line 293.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0024> created at line 293.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0030> created at line 293.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0044>.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0049> created at line 297.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0050>.
    Found 16-bit adder for signal <$share0000> created at line 293.
    Found 6-bit adder for signal <$share0005> created at line 260.
    Found 16-bit addsub for signal <$share0006> created at line 293.
    Found 32-bit subtractor for signal <$sub0000> created at line 520.
    Found 32-bit subtractor for signal <$sub0001> created at line 532.
    Found 32-bit subtractor for signal <$sub0002> created at line 544.
    Found 16-bit subtractor for signal <$sub0003> created at line 741.
a311 1
    Found 1-bit register for signal <intcyc>.
d330 1
a330 1
	inferred 228 D-type flip-flop(s).
d340 1
d342 1
d356 1
a356 1
# ROMs                                                 : 2
a357 1
 512x8-bit ROM                                         : 1
d374 2
a375 2
# Registers                                            : 54
 1-bit register                                        : 23
d381 1
a381 1
 8-bit register                                        : 21
d389 1
a389 2
# Multiplexers                                         : 20
 1-bit 4-to-1 multiplexer                              : 8
d394 2
a395 2
# Tristates                                            : 10
 8-bit tristate buffer                                 : 10
d406 1
a406 1
Analyzing FSM <FSM_1> for best encoding.
d414 6
a419 6
 00100 | 00000001001000000000000000000000
 00101 | 00010000001000000000000000000000
 00110 | 00000000001001000000000000000000
 00111 | 00000000001000100000000000000000
 01000 | 00000000001000010000000000000000
 01001 | 00000000001000001000000000000000
d421 1
a421 1
 01011 | 00000000001000000000010000000000
d425 1
a425 1
 01111 | 00000000000100000000000000000001
d428 1
a428 1
 10010 | 00000000001000000100000000000000
d430 1
a430 1
 10100 | 00000000001000000000000000010000
d434 2
a435 2
 11000 | 00000000001000000000000000000010
 11001 | 00000000000010000000000000000001
d440 1
a440 1
 11110 | 00100000001000000000000000000000
a441 9
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <intc/state> on signal <state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 00
 0001  | 01
 0010  | 11
-------------------
a442 2
INFO:Xst:1651 - Address input of ROM <rom/Mrom__mux0000> is tied to register <cpu/addr>.
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
d452 2
a453 2
# FSMs                                                 : 2
# RAMs                                                 : 2
a454 1
 512x8-bit single-port block RAM                       : 1
d473 2
a474 2
# Registers                                            : 319
 Flip-Flops                                            : 319
d482 1
a482 2
# Multiplexers                                         : 20
 1-bit 4-to-1 multiplexer                              : 8
d496 1
a496 1
WARNING:Xst:2040 - Unit testbench: 8 multi-source signals are replaced by logic (pull-up yes): N185, N187, N189, N1911, N193, N195, N197, N199.
d504 18
a521 6
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 69.
FlipFlop cpu/addr_0 has been replicated 2 time(s)
FlipFlop cpu/addr_1 has been replicated 2 time(s)
FlipFlop cpu/addr_2 has been replicated 2 time(s)
FlipFlop cpu/addr_3 has been replicated 1 time(s)
FlipFlop cpu/readio has been replicated 1 time(s)
d529 2
a530 2
# Registers                                            : 326
 Flip-Flops                                            : 326
d559 1
a559 1
# BELS                             : 3000
d561 1
a561 1
#      INV                         : 83
d563 9
a571 9
#      LUT2                        : 152
#      LUT2_D                      : 1
#      LUT2_L                      : 13
#      LUT3                        : 408
#      LUT3_D                      : 9
#      LUT3_L                      : 11
#      LUT4                        : 1358
#      LUT4_D                      : 13
#      LUT4_L                      : 66
d574 1
a574 1
#      MUXF5                       : 176
d578 3
a580 4
# FlipFlops/Latches                : 403
#      FDE                         : 214
#      FDE_1                       : 8
#      FDR                         : 22
d582 5
a586 6
#      FDRE_1                      : 42
#      FDRS                        : 29
#      FDRSE                       : 3
#      FDS                         : 2
#      FDSE                        : 1
#      LDCE                        : 53
d588 2
a589 2
# RAMS                             : 2
#      RAMB16_S9                   : 2
d593 1
a593 1
#      IBUF                        : 1
d595 1
a595 1
#      OBUF                        : 22
d603 3
a605 3
 Number of Slices:                    1196  out of   1920    62%  
 Number of Slice Flip Flops:           403  out of   3840    10%  
 Number of 4 input LUTs:              2253  out of   3840    58%  
d608 1
a608 1
 Number of BRAMs:                        2  out of     12    16%  
d624 1
a624 1
clock                                                | BUFGP                          | 326   |
d626 2
a627 2
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_5)| 11    |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_0)| 14    |
d629 1
a629 1
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/comp_4)| 14    |
d641 1
a641 1
reset                              | BUFGP                  | 53    |
d648 3
a650 3
   Minimum period: 18.139ns (Maximum Frequency: 55.130MHz)
   Minimum input arrival time before clock: 15.913ns
   Maximum output required time after clock: 18.039ns
d659 2
a660 2
  Clock period: 18.139ns (frequency: 55.130MHz)
  Total number of paths / destination ports: 22435 / 411
d662 3
a664 3
Delay:               9.069ns (Levels of Logic = 6)
  Source:            cpu/addr_10 (FF)
  Destination:       intc/active_7 (FF)
d666 1
a666 1
  Destination Clock: clock falling
d668 1
a668 1
  Data Path: cpu/addr_10 to intc/active_7
d672 12
a683 8
     FDE:C->Q              5   0.626   0.842  cpu/addr_10 (cpu/addr_10)
     LUT4:I2->O            1   0.479   0.000  select1/selectc/selectout1511 (N12307)
     MUXF5:I1->O           2   0.314   1.040  select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308)
     LUT4_D:I0->O          1   0.479   0.704  select1/selectc/selectout169_1 (select1/selectc/selectout169)
     LUT4:I3->O            9   0.479   1.014  intc/_and00011 (intc/_and0001)
     LUT4_D:I2->O          7   0.479   0.929  intc/_not00162 (N202)
     LUT4:I3->O            1   0.479   0.681  intc/_not0016 (intc/_not0016)
     FDRE_1:CE                 0.524          intc/active_7
d685 2
a686 2
    Total                      9.069ns (3.859ns logic, 5.211ns route)
                                       (42.5% logic, 57.5% route)
d690 1
a690 1
  Total number of paths / destination ports: 13926 / 607
d692 1
a692 1
Offset:              15.913ns (Levels of Logic = 11)
d694 1
a694 1
  Destination:       cpu/regfil_5_7 (FF)
d697 1
a697 1
  Data Path: data<4> to cpu/regfil_5_7
d701 11
a711 12
     IOBUF:IO->O         164   0.715   2.513  data_4_IOBUF (N11201)
     LUT2:I0->O           23   0.479   1.469  cpu/state_FFd1-In3282 (cpu/_cmp_eq0211)
     LUT4:I3->O           11   0.479   0.995  cpu/_cmp_eq00651 (cpu/_cmp_eq0065)
     LUT4:I3->O            8   0.479   0.980  cpu/_mux0012<0>311 (N447)
     LUT4:I2->O            1   0.479   0.851  cpu/_mux0013<7>1117_SW0 (N12113)
     LUT3_D:I1->O          2   0.479   1.040  cpu/_mux0013<7>1117 (N411)
     LUT4_D:I0->LO         1   0.479   0.159  cpu/_mux0013<7>1281 (N12420)
     LUT4:I2->O            8   0.479   1.216  cpu/_mux0013<7>120 (N410)
     LUT3:I0->O            1   0.479   0.851  cpu/_mux0013<7>8_SW0 (N11497)
     LUT4_L:I1->LO         1   0.479   0.159  cpu/_mux0013<7>22 (cpu/_mux0013<7>_map4164)
     LUT4:I2->O            1   0.479   0.000  cpu/_mux0013<7>172 (cpu/_mux0013<7>)
     FDE:D                     0.176          cpu/regfil_5_7
d713 2
a714 2
    Total                     15.913ns (5.681ns logic, 10.232ns route)
                                       (35.7% logic, 64.3% route)
d720 1
a720 1
Offset:              3.372ns (Levels of Logic = 1)
d729 2
a730 2
     IOBUF:IO->O         218   0.715   2.481  data_3_IOBUF (N11202)
     LDCE:D                    0.176          select1/selectd/comp_1
d732 2
a733 2
    Total                      3.372ns (0.891ns logic, 2.481ns route)
                                       (26.4% logic, 73.6% route)
d737 1
a737 1
  Total number of paths / destination ports: 14 / 14
d739 1
a739 1
Offset:              3.372ns (Levels of Logic = 1)
d748 1
a748 1
     IOBUF:IO->O         218   0.715   2.481  data_3_IOBUF (N11202)
d751 2
a752 2
    Total                      3.372ns (0.891ns logic, 2.481ns route)
                                       (26.4% logic, 73.6% route)
d758 1
a758 1
Offset:              3.372ns (Levels of Logic = 1)
d767 2
a768 2
     IOBUF:IO->O         218   0.715   2.481  data_3_IOBUF (N11202)
     LDCE:D                    0.176          select1/selectb/comp_1
d770 2
a771 2
    Total                      3.372ns (0.891ns logic, 2.481ns route)
                                       (26.4% logic, 73.6% route)
d777 1
a777 1
Offset:              3.372ns (Levels of Logic = 1)
d786 1
a786 1
     IOBUF:IO->O         218   0.715   2.481  data_3_IOBUF (N11202)
d789 2
a790 2
    Total                      3.372ns (0.891ns logic, 2.481ns route)
                                       (26.4% logic, 73.6% route)
d794 1
a794 1
  Total number of paths / destination ports: 1340 / 30
d796 2
a797 2
Offset:              17.890ns (Levels of Logic = 10)
  Source:            cpu/addr_10 (FF)
d801 1
a801 1
  Data Path: cpu/addr_10 to data<7>
d805 10
a814 11
     FDE:C->Q              5   0.626   0.842  cpu/addr_10 (cpu/addr_10)
     LUT4:I2->O            1   0.479   0.000  select1/selectc/selectout1511 (N12307)
     MUXF5:I1->O           2   0.314   1.040  select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308)
     LUT4_D:I0->O          1   0.479   0.704  select1/selectc/selectout169_1 (select1/selectc/selectout169)
     LUT4:I3->O            9   0.479   1.250  intc/_and00011 (intc/_and0001)
     LUT2:I0->O            8   0.479   1.216  intc/_or0000_inv1 (intc/_or0000_inv)
     LUT4:I0->O            1   0.479   0.704  N185LogicTrst1_SW0 (N4909)
     LUT4:I3->O           14   0.479   1.032  N185LogicTrst1 (N1913)
     LUT4:I3->O            1   0.479   0.740  N185LogicTrst136_SW1 (N12137)
     LUT4:I2->O            1   0.479   0.681  N185LogicTrst136 (data_7_IOBUF)
     IOBUF:I->IO               4.909          data_7_IOBUF (data<7>)
d816 2
a817 2
    Total                     17.890ns (9.681ns logic, 8.209ns route)
                                       (54.1% logic, 45.9% route)
d820 2
a821 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
  Total number of paths / destination ports: 552 / 8
d823 2
a824 2
Offset:              18.039ns (Levels of Logic = 10)
  Source:            select1/selectc/comp_0 (LATCH)
d826 1
a826 1
  Source Clock:      select1/selectc/_and0000 falling
d828 1
a828 1
  Data Path: select1/selectc/comp_0 to data<7>
d832 10
a841 11
     LDCE:G->Q             3   0.551   1.066  select1/selectc/comp_0 (select1/selectc/comp_0)
     LUT4:I0->O            1   0.479   0.000  select1/selectc/selectout1511 (N12307)
     MUXF5:I1->O           2   0.314   1.040  select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308)
     LUT4_D:I0->O          1   0.479   0.704  select1/selectc/selectout169_1 (select1/selectc/selectout169)
     LUT4:I3->O            9   0.479   1.250  intc/_and00011 (intc/_and0001)
     LUT2:I0->O            8   0.479   1.216  intc/_or0000_inv1 (intc/_or0000_inv)
     LUT4:I0->O            1   0.479   0.704  N185LogicTrst1_SW0 (N4909)
     LUT4:I3->O           14   0.479   1.032  N185LogicTrst1 (N1913)
     LUT4:I3->O            1   0.479   0.740  N185LogicTrst136_SW1 (N12137)
     LUT4:I2->O            1   0.479   0.681  N185LogicTrst136 (data_7_IOBUF)
     IOBUF:I->IO               4.909          data_7_IOBUF (data<7>)
d843 2
a844 2
    Total                     18.039ns (9.606ns logic, 8.433ns route)
                                       (53.3% logic, 46.7% route)
d848 1
a848 1
  Total number of paths / destination ports: 648 / 8
d850 2
a851 2
Offset:              15.904ns (Levels of Logic = 9)
  Source:            select1/selectb/comp_2 (LATCH)
d855 1
a855 1
  Data Path: select1/selectb/comp_2 to data<7>
d859 11
a869 10
     LDCE:G->Q             3   0.551   1.066  select1/selectb/comp_2 (select1/selectb/comp_2)
     LUT4:I0->O            1   0.479   0.000  select1/select2791 (N12279)
     MUXF5:I1->O           1   0.314   0.976  select1/select279_f5 (select1/select2_map1830)
     LUT4:I0->O            1   0.479   0.740  select1/select2169 (select1/select2_map1857)
     LUT4:I2->O            4   0.479   0.838  select1/select2195 (ramsel)
     LUT4:I2->O            1   0.479   0.704  N185LogicTrst1_SW0 (N4909)
     LUT4:I3->O           14   0.479   1.032  N185LogicTrst1 (N1913)
     LUT4:I3->O            1   0.479   0.740  N185LogicTrst136_SW1 (N12137)
     LUT4:I2->O            1   0.479   0.681  N185LogicTrst136 (data_7_IOBUF)
     IOBUF:I->IO               4.909          data_7_IOBUF (data<7>)
d871 1
a871 1
    Total                     15.904ns (9.127ns logic, 6.777ns route)
d876 1
a876 1
  Total number of paths / destination ports: 24 / 6
d878 3
a880 3
Offset:              13.765ns (Levels of Logic = 7)
  Source:            select1/selectd/datai_7 (LATCH)
  Destination:       data<7> (PAD)
d883 1
a883 26
  Data Path: select1/selectd/datai_7 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE_1:G->Q            1   0.551   0.704  select1/selectd/datai_7 (select1/selectd/datai_7)
     LUT4:I3->O            1   0.479   0.851  N185LogicTrst29_SW0 (N11753)
     LUT4:I1->O            1   0.479   0.740  N185LogicTrst29 (N185LogicTrst_map3906)
     LUT4:I2->O            1   0.479   0.976  N185LogicTrst60 (N185LogicTrst_map3910)
     LUT4:I0->O            1   0.479   0.740  N185LogicTrst93 (N185LogicTrst_map3916)
     LUT4:I2->O            1   0.479   0.740  N185LogicTrst136_SW1 (N12137)
     LUT4:I2->O            1   0.479   0.681  N185LogicTrst136 (data_7_IOBUF)
     IOBUF:I->IO               4.909          data_7_IOBUF (data<7>)
    ----------------------------------------
    Total                     13.765ns (8.334ns logic, 5.431ns route)
                                       (60.5% logic, 39.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
  Total number of paths / destination ports: 840 / 8
-------------------------------------------------------------------------
Offset:              16.261ns (Levels of Logic = 9)
  Source:            select1/selecta/mask_1 (LATCH)
  Destination:       data<7> (PAD)
  Source Clock:      select1/selecta/_and0000 falling

  Data Path: select1/selecta/mask_1 to data<7>
d887 7
a893 10
     LDCE:G->Q             6   0.551   1.148  select1/selecta/mask_1 (select1/selecta/mask_1)
     LUT4:I0->O            1   0.479   0.000  _and0000_inv181 (N12287)
     MUXF5:I1->O           1   0.314   0.976  _and0000_inv18_f5 (_and0000_inv_map1867)
     LUT4:I0->O            1   0.479   0.976  _and0000_inv108 (_and0000_inv_map1894)
     LUT4:I0->O           10   0.479   1.023  _and0000_inv211 (_and0000_inv)
     LUT3:I2->O            1   0.479   0.851  N185LogicTrst93_SW0 (N11757)
     LUT4:I1->O            1   0.479   0.740  N185LogicTrst93 (N185LogicTrst_map3916)
     LUT4:I2->O            1   0.479   0.740  N185LogicTrst136_SW1 (N12137)
     LUT4:I2->O            1   0.479   0.681  N185LogicTrst136 (data_7_IOBUF)
     IOBUF:I->IO               4.909          data_7_IOBUF (data<7>)
d895 2
a896 2
    Total                     16.261ns (9.127ns logic, 7.134ns route)
                                       (56.1% logic, 43.9% route)
d899 1
a899 1
CPU : 113.61 / 113.84 s | Elapsed : 114.00 / 114.00 s
d903 1
a903 1
Total memory usage is 200528 kilobytes
d906 2
a907 2
Number of warnings :   12 (   0 filtered)
Number of infos    :    5 (   0 filtered)
@


1.1.1.3
log
@8080 CPU project
@
text
@d4 1
a4 1
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
d7 1
a7 1
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
d38 1
a38 1
Target Device                      : xc3s1000-4-ft256
a98 8
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.
Architecture common of Entity common is up to date.
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.
Architecture vga_arch of Entity vga is up to date.
Architecture sync_arch of Entity sync is up to date.
Compiling verilog file "vgachr.v" in library work
Module <terminal> compiled
Module <chrmemmap> compiled
a99 1
Module <chrrom> compiled
a128 2
Analyzing hierarchy for module <terminal> in library <work>.

a132 27
Analyzing hierarchy for module <chrmemmap> in library <work>.

Analyzing hierarchy for entity <vga> in library <work> (architecture <vga_arch>) with generics.
	CLK_DIV = 4
	FIT_TO_SCREEN = true
	FREQ = 100000
	LINES_PER_FRAME = 480
	NUM_RGB_BITS = 3
	PIXEL_WIDTH = 1
	PIXELS_PER_LINE = 640

Analyzing hierarchy for module <chrrom> in library <work>.

Analyzing hierarchy for entity <sync> in library <work> (architecture <sync_arch>) with generics.
	FREQ = 25000
	PERIOD = 32
	START = 26
	VISIBLE = 640
	WIDTH = 4

Analyzing hierarchy for entity <sync> in library <work> (architecture <sync_arch>) with generics.
	FREQ = 31
	PERIOD = 16784
	START = 15700
	VISIBLE = 480
	WIDTH = 64

a161 35
Analyzing module <terminal> in library <work>.
Module <terminal> is correct for synthesis.
 
Analyzing module <chrmemmap> in library <work>.
Module <chrmemmap> is correct for synthesis.
 
Analyzing generic Entity <vga> in library <work> (Architecture <vga_arch>).
	PIXELS_PER_LINE = 640
	CLK_DIV = 4
	FIT_TO_SCREEN = true
	FREQ = 100000
	LINES_PER_FRAME = 480
	NUM_RGB_BITS = 3
	PIXEL_WIDTH = 1
Entity <vga> analyzed. Unit <vga> generated.

Analyzing generic Entity <sync.1> in library <work> (Architecture <sync_arch>).
	PERIOD = 32
	WIDTH = 4
	START = 26
	VISIBLE = 640
	FREQ = 25000
Entity <sync.1> analyzed. Unit <sync.1> generated.

Analyzing generic Entity <sync.2> in library <work> (Architecture <sync_arch>).
	FREQ = 31
	PERIOD = 16784
	START = 15700
	VISIBLE = 480
	WIDTH = 64
Entity <sync.2> analyzed. Unit <sync.2> generated.

Analyzing module <chrrom> in library <work>.
Module <chrrom> is correct for synthesis.
 
d168 1
a168 1
INFO:Xst:1304 - Contents of register <cmread> in unit <terminal> never changes during circuit operation. The register is replaced by logic.
d172 1
a172 1
    Found 128x8-bit ROM for signal <$mux0000>.
d250 1
a250 1
    Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 301.
d262 7
a268 7
    Found 5-bit adder for signal <$add0001> created at line 1484.
    Found 8-bit adder carry out for signal <$addsub0000> created at line 1477.
    Found 4-bit adder carry out for signal <$addsub0001> created at line 1478.
    Found 6-bit subtractor for signal <$sub0000> created at line 1490.
    Found 6-bit subtractor for signal <$sub0001> created at line 1496.
    Found 9-bit subtractor for signal <$sub0002> created at line 1489.
    Found 8-bit xor2 for signal <$xor0000> created at line 1507.
a276 34
Synthesizing Unit <chrrom>.
    Related source file is "vgachr.v".
    Found 2048x8-bit ROM for signal <data>.
    Summary:
	inferred   1 ROM(s).
Unit <chrrom> synthesized.


Synthesizing Unit <sync_1>.
    Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
    Found 16-bit adder for signal <$addsub0000> created at line 396.
    Found 1-bit register for signal <blank_r>.
    Found 16-bit register for signal <cnt_r>.
    Found 1-bit register for signal <gate_r>.
    Found 1-bit register for signal <sync_r>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <sync_1> synthesized.


Synthesizing Unit <sync_2>.
    Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
    Found 16-bit adder for signal <$addsub0000> created at line 396.
    Found 1-bit register for signal <blank_r>.
    Found 16-bit register for signal <cnt_r>.
    Found 1-bit register for signal <gate_r>.
    Found 1-bit register for signal <sync_r>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <sync_2> synthesized.


d295 2
a296 2
    | States             | 31                                             |
    | Transitions        | 900                                            |
d298 1
a298 1
    | Outputs            | 33                                             |
d306 1
a306 1
    Found 4x1-bit ROM for signal <$mux0043> created at line 301.
d314 9
a322 9
    Found 32-bit adder for signal <$add0001> created at line 483.
    Found 32-bit adder for signal <$add0002> created at line 495.
    Found 32-bit adder for signal <$add0003> created at line 507.
    Found 16-bit adder for signal <$add0004> created at line 967.
    Found 16-bit adder for signal <$add0005> created at line 878.
    Found 32-bit adder for signal <$add0006> created at line 552.
    Found 32-bit adder for signal <$add0007> created at line 540.
    Found 32-bit adder for signal <$add0008> created at line 528.
    Found 17-bit adder for signal <$add0009> created at line 473.
d330 2
a331 2
    Found 16-bit adder for signal <$addsub0007> created at line 1038.
    Found 16-bit adder for signal <$addsub0008> created at line 1079.
d333 1
a333 1
    Found 4-bit adder carry out for signal <$addsub0010> created at line 348.
d335 16
a350 16
    Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 345.
    Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1294.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0022> created at line 301.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0023> created at line 301.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 301.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 301.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0045>.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0050> created at line 305.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0051>.
    Found 16-bit adder for signal <$share0000> created at line 301.
    Found 6-bit adder for signal <$share0005> created at line 262.
    Found 16-bit addsub for signal <$share0006> created at line 301.
    Found 32-bit subtractor for signal <$sub0000> created at line 528.
    Found 32-bit subtractor for signal <$sub0001> created at line 540.
    Found 32-bit subtractor for signal <$sub0002> created at line 552.
    Found 16-bit subtractor for signal <$sub0003> created at line 749.
a359 1
    Found 1-bit register for signal <eienb>.
a360 1
    Found 8-bit register for signal <opcode>.
d379 1
a379 1
	inferred 237 D-type flip-flop(s).
d387 3
a389 70
Synthesizing Unit <vga>.
    Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
WARNING:Xst:646 - Signal <line_cnt> is assigned but never used.
WARNING:Xst:646 - Signal <pixel_cnt<15:4>> is assigned but never used.
    Found 3-bit register for signal <blank_r>.
    Found 1-bit register for signal <cke>.
    Found 8-bit up counter for signal <clk_div_cnt>.
    Found 1-bit register for signal <eof_r>.
    Found 3-bit register for signal <hsync_r>.
    Found 16-bit register for signal <pixel_data_r>.
    Found 1-bit register for signal <rd_r>.
    Found 9-bit register for signal <rgb_r>.
    Summary:
	inferred   1 Counter(s).
	inferred  34 D-type flip-flop(s).
Unit <vga> synthesized.


Synthesizing Unit <chrmemmap>.
    Related source file is "vgachr.v".
WARNING:Xst:646 - Signal <blank> is assigned but never used.
    Found 1920x8-bit single-port block RAM for signal <scnbuf>.
    -----------------------------------------------------------------------
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1920-word x 8-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <write>         | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <data>          |          |
    |     doA            | connected to signal <datao>         |          |
    -----------------------------------------------------------------------
    Found 1920x8-bit dual-port distributed RAM for signal <scnbuf>.
    -----------------------------------------------------------------------
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1920-word x 8-bit                   |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <write>         | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <data>          |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 1920-word x 8-bit                   |          |
    |     addrB          | connected to internal node          |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <fchsta> of Case statement line 320 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <fchsta> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found finite state machine <FSM_2> for signal <fchsta>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 4                                              |
    | Inputs             | 0                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $or0000 (positive)                             |
    | Reset              | $or0001 (positive)                             |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:643 - "vgachr.v" line 361: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
a390 13
    Found 9-bit subtractor for signal <$addsub0000> created at line 361.
    Found 11-bit adder for signal <$addsub0001> created at line 361.
    Found 7-bit comparator greatequal for signal <$cmp_ge0000> created at line 301.
    Found 5-bit comparator greatequal for signal <$cmp_ge0001> created at line 305.
    Found 7-bit comparator less for signal <$cmp_lt0000> created at line 301.
    Found 5-bit comparator less for signal <$cmp_lt0001> created at line 305.
    Found 8-bit comparator less for signal <$cmp_lt0002> created at line 361.
    Found 9x6-bit multiplier for signal <$mult0002> created at line 361.
    Found 7-bit up counter for signal <chrcnt>.
    Found 5-bit up counter for signal <lincnt>.
    Found 16-bit register for signal <pixeldata>.
    Found 5-bit up counter for signal <rowcnt>.
    Found 11-bit up accumulator for signal <scnadr>.
a391 8
	inferred   1 Finite State Machine(s).
	inferred   2 RAM(s).
	inferred   3 Counter(s).
	inferred   1 Accumulator(s).
	inferred  16 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred   5 Comparator(s).
a392 48
Unit <chrmemmap> synthesized.


Synthesizing Unit <terminal>.
    Related source file is "vgachr.v".
    Found finite state machine <FSM_3> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 12                                             |
    | Inputs             | 5                                              |
    | Outputs            | 7                                              |
    | Clock              | clock (falling_edge)                           |
    | Clock enable       | $or0000 (negative)                             |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000011                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <data>.
    Found 11-bit adder for signal <$addsub0000> created at line 175.
    Found 11-bit adder for signal <$addsub0001> created at line 208.
    Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 143.
    Found 11-bit comparator less for signal <$cmp_lt0000> created at line 206.
    Found 8-bit register for signal <chrdatw>.
    Found 11-bit register for signal <cmaddr>.
    Found 8-bit tristate buffer for signal <cmdata>.
    Found 1-bit register for signal <cmdatae>.
    Found 8-bit register for signal <cmdatai>.
    Found 1-bit register for signal <cmwrite>.
    Found 11-bit register for signal <cursor>.
    Found 8-bit register for signal <datao>.
    Found 1-bit register for signal <outrdy>.
    Found 1-bit register for signal <wrtchr>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  50 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred  16 Tristate(s).
Unit <terminal> synthesized.


Synthesizing Unit <testbench>.
    Related source file is "testbench.v".
    Found 8-bit up counter for signal <clkdiv>.
    Summary:
	inferred   1 Counter(s).
d401 1
a401 1
# RAMs                                                 : 2
d403 1
a403 4
 1920x8-bit dual-port distributed RAM                  : 1
# ROMs                                                 : 3
 128x8-bit ROM                                         : 1
 2048x8-bit ROM                                        : 1
d405 3
a407 5
# Multipliers                                          : 1
 9x6-bit multiplier                                    : 1
# Adders/Subtractors                                   : 49
 11-bit adder                                          : 4
 16-bit adder                                          : 7
d421 4
a424 11
 9-bit subtractor                                      : 3
# Counters                                             : 5
 5-bit up counter                                      : 2
 7-bit up counter                                      : 1
 8-bit up counter                                      : 2
# Accumulators                                         : 1
 11-bit up accumulator                                 : 1
# Registers                                            : 81
 1-bit register                                        : 37
 11-bit register                                       : 2
 16-bit register                                       : 9
d426 1
a426 1
 3-bit register                                        : 4
d429 1
a429 2
 8-bit register                                        : 25
 9-bit register                                        : 1
d433 1
a433 2
# Comparators                                          : 14
 11-bit comparator less                                : 1
a435 2
 5-bit comparator greatequal                           : 1
 5-bit comparator less                                 : 1
a436 4
 7-bit comparator greatequal                           : 1
 7-bit comparator less                                 : 1
 8-bit comparator greatequal                           : 1
 8-bit comparator less                                 : 1
d443 2
a444 3
# Tristates                                            : 19
 1-bit tristate buffer                                 : 8
 8-bit tristate buffer                                 : 11
a454 23
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <adm3a/state> on signal <state[1:3]> with sequential encoding.
--------------------
 State  | Encoding
--------------------
 000000 | 010
 000001 | 001
 000010 | 011
 000011 | 000
 000100 | 100
 000101 | 101
 000110 | 110
--------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <adm3a/display/fchsta> on signal <fchsta[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------
d456 2
a457 2
Optimizing FSM <cpu/state> on signal <state[1:33]> with speed1 encoding.
--------------------------------------------
d459 32
a490 33
--------------------------------------------
 00001 | 010000000000000000000000000000000
 00010 | 001000000000000000000000000000000
 00011 | 000100000000000000000000000000000
 00100 | 000000001000000000000000000000000
 00101 | 000000000100000000000000000000001
 00110 | 000001000000000000000000000000001
 00111 | 000000000000001000000000000000001
 01000 | 000000000000000100000000000000001
 01001 | 000000000000000001000000000000001
 01010 | 000000000000000000100000000000001
 01011 | 100000000000000010000000000000000
 01100 | 000000000000000000000001000000001
 01101 | 000000100000000000000000000000000
 01110 | 000000000010000000000000000000000
 01111 | 000000000001000000000000000000000
 10000 | 100000000000100000000000000000000
 10001 | 000000010000000000000000000000000
 10010 | 000000000000000000000000000010000
 10011 | 000000000000000000010000000000001
 10100 | 000000000000000000000000010000000
 10101 | 000000000000000000000000000001001
 10110 | 000000000000000000000000000100000
 10111 | 000000000000000000000000000000100
 11000 | 000000000000000000000000000000010
 11001 | 000000000000000000000000001000001
 11010 | 100000000000010000000000000000000
 11011 | 100000000000000000001000000000000
 11100 | 100000000000000000000010000000000
 11101 | 100000000000000000000000100000000
 11110 | 000000000000000000000100000000000
 11111 | 000010000000000000000000000000001
--------------------------------------------
d500 1
a500 2
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
WARNING:Xst:2404 -  FFs/Latches <chrdatw<7:7>> (without init value) have a constant value of 0 in block <terminal>.
a502 1
INFO:Xst:2261 - The FF/Latch <rgb_r_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <rgb_r_1> <rgb_r_2> <rgb_r_3> <rgb_r_4> <rgb_r_5> <rgb_r_6> <rgb_r_7> <rgb_r_8> 
a506 9
WARNING:Xst:1710 - FF/Latch  <datao_0> (without init value) has a constant value of 0 in block <terminal>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datao_1> (without init value) has a constant value of 0 in block <terminal>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datao_2> (without init value) has a constant value of 0 in block <terminal>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datao_3> (without init value) has a constant value of 0 in block <terminal>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datao_4> (without init value) has a constant value of 0 in block <terminal>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datao_5> (without init value) has a constant value of 0 in block <terminal>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datao_6> (without init value) has a constant value of 0 in block <terminal>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cmdatai_7> (without init value) has a constant value of 0 in block <terminal>.
WARNING:Xst:1291 - FF/Latch <blank_r_3> is unconnected in block <vgai>.
d512 2
a513 2
# FSMs                                                 : 4
# RAMs                                                 : 3
d515 2
a516 4
 128x8-bit single-port block RAM                       : 1
 1920x8-bit dual-port distributed RAM                  : 1
# ROMs                                                 : 2
 2048x8-bit ROM                                        : 1
d518 2
a519 5
# Multipliers                                          : 1
 9x6-bit multiplier                                    : 1
# Adders/Subtractors                                   : 49
 11-bit adder                                          : 4
 16-bit adder                                          : 7
d533 3
a535 9
 9-bit subtractor                                      : 3
# Counters                                             : 5
 5-bit up counter                                      : 2
 7-bit up counter                                      : 1
 8-bit up counter                                      : 2
# Accumulators                                         : 1
 11-bit up accumulator                                 : 1
# Registers                                            : 455
 Flip-Flops                                            : 455
d539 1
a539 2
# Comparators                                          : 14
 11-bit comparator less                                : 1
a541 2
 5-bit comparator greatequal                           : 1
 5-bit comparator less                                 : 1
a542 4
 7-bit comparator greatequal                           : 1
 7-bit comparator less                                 : 1
 8-bit comparator greatequal                           : 1
 8-bit comparator less                                 : 1
d558 1
a558 141
WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0000>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_4> and unit <LPM_COMPARE_6> are dual, second instance is removed
WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_7> are dual, second instance is removed
WARNING:Xst:1291 - FF/Latch <lincnt_0> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <lincnt_1> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <lincnt_2> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <lincnt_3> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <lincnt_4> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8401> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8411> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8441> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8421> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8431> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8451> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8461> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8471> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8481> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8491> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8501> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8511> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8521> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8531> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8541> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8551> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8561> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8571> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8581> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8591> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8601> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8611> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8621> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8631> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8641> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8651> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8661> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8671> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8681> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8691> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8701> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8711> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8721> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8751> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8731> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8741> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8761> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8771> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8781> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8791> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8801> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8811> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8821> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8831> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8841> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8851> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8861> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8871> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8881> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8891> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8901> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8911> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8921> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8931> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8941> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8951> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8961> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8971> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8981> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8991> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9001> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9011> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9021> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9031> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9061> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9041> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9051> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9071> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9081> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9091> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9101> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9111> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9121> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9131> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9141> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9151> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9161> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9171> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9181> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9191> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9201> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9211> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9221> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9231> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9241> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9251> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9261> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9271> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9281> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9291> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9301> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9311> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9321> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9331> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9341> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9371> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9351> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9361> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9381> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9391> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9401> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9411> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9421> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9431> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9441> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9451> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9461> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9471> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9481> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9491> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9521> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9501> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9511> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9531> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9541> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9551> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9561> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9571> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9581> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9591> is unconnected in block <chrmemmap>.
WARNING:Xst:1710 - FF/Latch  <pixeldata_0> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <pixeldata_7> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <pixeldata_8> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <pixeldata_15> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <scnadr_0> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <scnadr_1> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <scnadr_2> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <scnadr_3> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <clkdiv_4> is unconnected in block <testbench>.
WARNING:Xst:1291 - FF/Latch <clkdiv_5> is unconnected in block <testbench>.
WARNING:Xst:1291 - FF/Latch <clkdiv_6> is unconnected in block <testbench>.
WARNING:Xst:1291 - FF/Latch <clkdiv_7> is unconnected in block <testbench>.
WARNING:Xst:2040 - Unit testbench: 16 multi-source signals are replaced by logic (pull-up yes): adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N187, N189, N1911, N193, N195, N197, N199, N2011.
WARNING:Xst:2042 - Unit chrmemmap: 8 internal tristates are replaced by logic (pull-up yes): data<0>, data<1>, data<2>, data<3>, data<4>, data<5>, data<6>, data<7>.
a561 6
Optimizing unit <sync_2> ...

Optimizing unit <sync_1> ...

Optimizing unit <vga> ...

a564 2
WARNING:Xst:1710 - FF/Latch  <adm3a/display/vgai/pixel_data_r_15> (without init value) has a constant value of 0 in block <testbench>.
WARNING:Xst:1291 - FF/Latch <adm3a/display/vgai/blank_r_3> is unconnected in block <testbench>.
d566 4
a569 12
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 28.
FlipFlop adm3a/cmaddr_0 has been replicated 5 time(s)
FlipFlop adm3a/cmaddr_1 has been replicated 5 time(s)
FlipFlop adm3a/cmaddr_2 has been replicated 5 time(s)
FlipFlop adm3a/cmaddr_3 has been replicated 5 time(s)
FlipFlop adm3a/display/chrcnt_0 has been replicated 76 time(s)
FlipFlop adm3a/display/chrcnt_1 has been replicated 76 time(s)
FlipFlop adm3a/display/chrcnt_2 has been replicated 76 time(s)
FlipFlop adm3a/display/chrcnt_3 has been replicated 76 time(s)
FlipFlop adm3a/display/chrcnt_4 has been replicated 2 time(s)
FlipFlop adm3a/display/scnadr_4 has been replicated 3 time(s)
FlipFlop cpu/addr_2 has been replicated 1 time(s)
d571 1
a574 5
Processing Unit <testbench> :
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/display/vgai/blank_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <adm3a/display/vgai/hsync_r_3> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <testbench> processed.

d579 2
a580 2
# Registers                                            : 811
 Flip-Flops                                            : 811
d606 1
a606 1
# IOs                              : 44
d609 1
a609 1
# BELS                             : 5813
d611 11
a621 11
#      INV                         : 95
#      LUT1                        : 189
#      LUT2                        : 360
#      LUT2_D                      : 9
#      LUT2_L                      : 3
#      LUT3                        : 1100
#      LUT3_D                      : 7
#      LUT3_L                      : 3
#      LUT4                        : 2221
#      LUT4_D                      : 55
#      LUT4_L                      : 41
d623 3
a625 5
#      MUXCY                       : 575
#      MUXF5                       : 586
#      MUXF6                       : 167
#      MUXF7                       : 55
#      MUXF8                       : 23
d627 9
a635 14
#      XORCY                       : 294
# FlipFlops/Latches                : 899
#      FD                          : 4
#      FDC                         : 9
#      FDCE                        : 53
#      FDE                         : 230
#      FDE_1                       : 54
#      FDP                         : 1
#      FDPE                        : 7
#      FDR                         : 23
#      FDRE                        : 335
#      FDRE_1                      : 60
#      FDRS                        : 30
#      FDRSE                       : 2
d638 3
a640 4
#      LDCE                        : 56
#      LDE_1                       : 32
# RAMS                             : 842
#      RAM16X1D                    : 840
d642 1
a642 2
# Clock Buffers                    : 3
#      BUFG                        : 1
d644 1
a644 1
# IO Buffers                       : 42
d647 1
a647 3
#      OBUF                        : 33
# MULTs                            : 1
#      MULT18X18                   : 1
d653 1
a653 1
Selected Device : 3s1000ft256-4 
d655 7
a661 10
 Number of Slices:                    2130  out of   7680    27%  
 Number of Slice Flip Flops:           899  out of  15360     5%  
 Number of 4 input LUTs:              5763  out of  15360    37%  
    Number used as logic:             4083
    Number used as RAMs:              1680
 Number of IOs:                         44
 Number of bonded IOBs:                 44  out of    173    25%  
 Number of BRAMs:                        2  out of     24     8%  
 Number of MULT18X18s:                   1  out of     24     4%  
 Number of GCLKs:                        3  out of      8    37%  
d676 6
a681 7
clkdiv_31                                            | BUFG                           | 331   |
clock                                                | BUFGP                          | 1320  |
reset_n                                              | BUFGP                          | 32    |
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/comp_5)| 14    |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_3)| 14    |
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/comp_4)| 14    |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/mask_6)| 14    |
d690 5
a694 5
-----------------------------------+----------------------------------------------------+-------+
Control Signal                     | Buffer(FF name)                                    | Load  |
-----------------------------------+----------------------------------------------------+-------+
reset(reset1_INV_0:O)              | NONE(adm3a/display/vgai/gen_syncs_fit.hsync/sync_r)| 126   |
-----------------------------------+----------------------------------------------------+-------+
d698 1
a698 1
Speed Grade: -4
d700 3
a702 3
   Minimum period: 33.473ns (Maximum Frequency: 29.875MHz)
   Minimum input arrival time before clock: 10.291ns
   Maximum output required time after clock: 19.654ns
a709 28
Timing constraint: Default period analysis for Clock 'clkdiv_31'
  Clock period: 24.368ns (frequency: 41.037MHz)
  Total number of paths / destination ports: 40013 / 419
-------------------------------------------------------------------------
Delay:               12.184ns (Levels of Logic = 7)
  Source:            cpu/addr_4 (FF)
  Destination:       intc/datai_6 (FF)
  Source Clock:      clkdiv_31 rising
  Destination Clock: clkdiv_31 falling

  Data Path: cpu/addr_4 to intc/datai_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              8   0.720   1.278  cpu/addr_4 (cpu/addr_4)
     LUT4:I1->O            1   0.551   0.000  select1/selectc/selectout791 (N14518)
     MUXF5:I1->O           1   0.360   1.140  select1/selectc/selectout79_f5 (select1/selectc/selectout_map4980)
     LUT4_D:I0->O          3   0.551   0.975  select1/selectc/selectout169 (select1/selectc/selectout_map5007)
     LUT4:I2->O           25   0.551   2.008  intc/_not0027_SW0 (intc/_and0001)
     LUT4_D:I1->O          6   0.551   1.198  intc/_mux0008<4>1 (N19)
     LUT4:I1->O            1   0.551   0.996  intc/_mux0008<7>12 (intc/_mux0008<7>_map4950)
     LUT4:I1->O            1   0.551   0.000  intc/_mux0008<7>33 (intc/_mux0008<7>)
     FDE_1:D                   0.203          intc/datai_7
    ----------------------------------------
    Total                     12.184ns (4.589ns logic, 7.595ns route)
                                       (37.7% logic, 62.3% route)

=========================================================================
d711 2
a712 2
  Clock period: 33.473ns (frequency: 29.875MHz)
  Total number of paths / destination ports: 158202401 / 9605
d714 3
a716 3
Delay:               33.473ns (Levels of Logic = 26)
  Source:            adm3a/display/scnadr_4_1 (FF)
  Destination:       adm3a/display/pixeldata_5 (FF)
d718 1
a718 46
  Destination Clock: clock rising

  Data Path: adm3a/display/scnadr_4_1 to adm3a/display/pixeldata_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   0.720   1.216  adm3a/display/scnadr_4_1 (adm3a/display/scnadr_4_1)
     LUT2:I0->O            1   0.551   0.000  adm3a/display/Madd__COND_40_lut<4>_1 (adm3a/display/Madd__COND_40_lut<4>)
     MUXCY:S->O            1   0.500   0.000  adm3a/display/Madd__COND_40_cy<4> (adm3a/display/Madd__COND_40_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  adm3a/display/Madd__COND_40_cy<5> (adm3a/display/Madd__COND_40_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  adm3a/display/Madd__COND_40_cy<6> (adm3a/display/Madd__COND_40_cy<6>)
     XORCY:CI->O         392   0.904   3.983  adm3a/display/Madd__COND_40_xor<7> (adm3a/display/_COND_40<7>)
     LUT3:I2->O            1   0.551   0.000  adm3a/display/_COND_40<7>23 (adm3a/display/N251234567)
     MUXF5:I0->O           1   0.360   0.000  adm3a/display/_COND_40<4>_f5_10 (adm3a/display/_COND_40<4>_f511)
     MUXF6:I0->O           1   0.342   0.996  adm3a/display/_COND_40<5>_f6_4 (adm3a/display/_COND_40<5>_f65)
     LUT3:I1->O            1   0.551   0.000  adm3a/display/_COND_40<8>1_F (N13708)
     MUXF5:I0->O           1   0.360   0.869  adm3a/display/_COND_40<8>1 (adm3a/display/_COND_40<8>11)
     LUT3:I2->O            1   0.551   0.000  adm3a/display/inst_LPM_MUX_f5_G (N13663)
     MUXF5:I1->O           3   0.360   0.907  adm3a/display/inst_LPM_MUX_f5 (adm3a/display/curchr<0>)
     MULT18X18:A0->P0     51   1.779   2.157  adm3a/display/Mmult__mult0002 (adm3a/display/_mult0002<0>)
     LUT2:I1->O            1   0.551   0.000  adm3a/display/Madd__addsub0001_lut<0> (adm3a/display/N2558)
     MUXCY:S->O            1   0.500   0.000  adm3a/display/Madd__addsub0001_cy<0> (adm3a/display/Madd__addsub0001_cy<0>)
     XORCY:CI->O         176   0.904   2.704  adm3a/display/Madd__addsub0001_xor<1> (adm3a/display/_addsub0001<1>)
     LUT4_D:I3->O         17   0.551   1.371  adm3a/display/crom/Mrom_data349_SW0 (N12990)
     LUT4:I3->O            7   0.551   1.092  adm3a/display/crom/Mrom_data51 (adm3a/display/N53)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/chradr<5>_f5_02_F (N14386)
     MUXF5:I0->O           1   0.360   0.827  adm3a/display/chradr<5>_f5_02 (adm3a/display/chradr<5>_f51123)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/chradr<8>489_G (N13703)
     MUXF5:I1->O           1   0.360   0.869  adm3a/display/chradr<8>489 (adm3a/display/chradr<8>4_map4807)
     LUT4:I2->O            1   0.551   0.827  adm3a/display/chradr<8>491 (adm3a/display/chradr<8>112)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/mux2_f5_G (N13675)
     MUXF5:I1->O           2   0.360   0.903  adm3a/display/mux2_f5 (adm3a/display/N13612)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/_mux0000<5>1 (adm3a/display/_mux0000<5>)
     FDE:D                     0.203          adm3a/display/pixeldata_5
    ----------------------------------------
    Total                     33.473ns (14.752ns logic, 18.721ns route)
                                       (44.1% logic, 55.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkdiv_31'
  Total number of paths / destination ports: 462 / 433
-------------------------------------------------------------------------
Offset:              10.291ns (Levels of Logic = 7)
  Source:            waitr (PAD)
  Destination:       cpu/state_FFd2 (FF)
  Destination Clock: clkdiv_31 rising
d720 1
a720 1
  Data Path: waitr to cpu/state_FFd2
d724 8
a731 8
     IBUF:I->O            13   0.821   1.365  waitr_IBUF (waitr_IBUF)
     LUT4:I1->O            1   0.551   0.827  cpu/state_FFd8-In8_SW0 (N1768)
     LUT4:I3->O            3   0.551   0.975  cpu/state_FFd8-In8 (N265)
     LUT4:I2->O            1   0.551   1.140  cpu/state_FFd2-In20 (cpu/state_FFd2-In_map3973)
     LUT4:I0->O            1   0.551   0.827  cpu/state_FFd2-In201 (cpu/state_FFd2-In_map4015)
     LUT4:I3->O            1   0.551   0.827  cpu/state_FFd2-In419 (cpu/state_FFd2-In_map4064)
     LUT4:I3->O            1   0.551   0.000  cpu/state_FFd2-In435 (cpu/state_FFd2-In)
     FDS:D                     0.203          cpu/state_FFd2
d733 2
a734 2
    Total                     10.291ns (4.330ns logic, 5.961ns route)
                                       (42.1% logic, 57.9% route)
d738 1
a738 1
  Total number of paths / destination ports: 413 / 413
d740 3
a742 3
Offset:              10.229ns (Levels of Logic = 3)
  Source:            reset_n (PAD)
  Destination:       adm3a/display/chrcnt_0 (FF)
d745 1
a745 1
  Data Path: reset_n to adm3a/display/chrcnt_0
d749 12
a760 4
     BUFGP:I->O          177   0.401   3.023  reset_n_BUFGP (reset_n_BUFGP)
     LUT3:I0->O           15   0.551   1.214  adm3a/display/_or00011 (adm3a/display/_or0001)
     LUT4:I3->O          313   0.551   3.463  adm3a/display/_or00021 (adm3a/display/_or0002)
     FDRE:R                    1.026          adm3a/display/chrcnt_0
d762 2
a763 2
    Total                     10.229ns (2.529ns logic, 7.700ns route)
                                       (24.7% logic, 75.3% route)
d767 1
a767 1
  Total number of paths / destination ports: 14 / 14
d769 3
a771 3
Offset:              2.474ns (Levels of Logic = 1)
  Source:            data<6> (PAD)
  Destination:       select1/selectd/mask_6 (LATCH)
d774 1
a774 1
  Data Path: data<6> to select1/selectd/mask_6
d778 2
a779 2
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N12692)
     LDCE:D                    0.203          select1/selectd/mask_6
d781 2
a782 2
    Total                      2.474ns (1.024ns logic, 1.450ns route)
                                       (41.4% logic, 58.6% route)
d788 3
a790 3
Offset:              2.474ns (Levels of Logic = 1)
  Source:            data<6> (PAD)
  Destination:       select1/selectc/mask_6 (LATCH)
d793 1
a793 1
  Data Path: data<6> to select1/selectc/mask_6
d797 2
a798 2
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N12692)
     LDCE:D                    0.203          select1/selectc/mask_6
d800 2
a801 2
    Total                      2.474ns (1.024ns logic, 1.450ns route)
                                       (41.4% logic, 58.6% route)
d807 3
a809 3
Offset:              2.474ns (Levels of Logic = 1)
  Source:            data<6> (PAD)
  Destination:       select1/selectb/mask_6 (LATCH)
d812 1
a812 1
  Data Path: data<6> to select1/selectb/mask_6
d816 2
a817 2
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N12692)
     LDCE:D                    0.203          select1/selectb/mask_6
d819 2
a820 2
    Total                      2.474ns (1.024ns logic, 1.450ns route)
                                       (41.4% logic, 58.6% route)
d826 3
a828 3
Offset:              2.474ns (Levels of Logic = 1)
  Source:            data<6> (PAD)
  Destination:       select1/selecta/mask_6 (LATCH)
d831 1
a831 1
  Data Path: data<6> to select1/selecta/mask_6
d835 2
a836 2
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N12692)
     LDCE:D                    0.203          select1/selecta/mask_6
d838 2
a839 2
    Total                      2.474ns (1.024ns logic, 1.450ns route)
                                       (41.4% logic, 58.6% route)
d842 2
a843 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv_31'
  Total number of paths / destination ports: 2213 / 30
d845 2
a846 2
Offset:              19.654ns (Levels of Logic = 8)
  Source:            cpu/addr_4 (FF)
d848 1
a848 1
  Source Clock:      clkdiv_31 rising
d850 1
a850 1
  Data Path: cpu/addr_4 to data<7>
d854 11
a864 9
     FDE:C->Q              8   0.720   1.278  cpu/addr_4 (cpu/addr_4)
     LUT4:I1->O            3   0.551   1.246  select1/selacc426 (select1/selacc4_map4116)
     LUT2:I0->O            3   0.551   1.246  select1/selacc454 (select1/selacc)
     LUT4:I0->O            9   0.551   1.319  select1/selecta/_and0001_inv1 (select1/selecta/_and0001_inv)
     LUT2:I1->O            1   0.551   1.140  N187LogicTrst119 (N187LogicTrst1_map4664)
     LUT4:I0->O            1   0.551   0.827  N187LogicTrst124 (N187LogicTrst1_map4665)
     LUT4:I3->O           16   0.551   1.576  N187LogicTrst141 (N190)
     LUT3:I0->O            1   0.551   0.801  N187LogicTrst1211 (data_7_IOBUF)
     IOBUF:I->IO               5.644          data_7_IOBUF (data<7>)
d866 2
a867 2
    Total                     19.654ns (10.221ns logic, 9.433ns route)
                                       (52.0% logic, 48.0% route)
d870 2
a871 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  Total number of paths / destination ports: 12 / 12
d873 2
a874 2
Offset:              13.243ns (Levels of Logic = 5)
  Source:            adm3a/datao_7 (FF)
d876 1
a876 1
  Source Clock:      clock falling
d878 1
a878 1
  Data Path: adm3a/datao_7 to data<7>
d882 11
a892 6
     FDE_1:C->Q            1   0.720   0.869  adm3a/datao_7 (adm3a/datao_7)
     LUT4:I2->O            1   0.551   0.996  N187LogicTrst69 (N187LogicTrst_map4691)
     LUT3:I1->O            1   0.551   1.140  N187LogicTrst109_SW0 (N14179)
     LUT4:I0->O            1   0.551   0.869  N187LogicTrst109 (N187LogicTrst_map4696)
     LUT3:I2->O            1   0.551   0.801  N187LogicTrst1211 (data_7_IOBUF)
     IOBUF:I->IO               5.644          data_7_IOBUF (data<7>)
d894 2
a895 2
    Total                     13.243ns (8.568ns logic, 4.675ns route)
                                       (64.7% logic, 35.3% route)
d899 1
a899 1
  Total number of paths / destination ports: 840 / 8
d901 2
a902 2
Offset:              17.126ns (Levels of Logic = 8)
  Source:            select1/selectb/comp_1 (LATCH)
d906 1
a906 27
  Data Path: select1/selectb/comp_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.633   1.246  select1/selectb/comp_1 (select1/selectb/comp_1)
     LUT4:I0->O            1   0.551   0.000  select1/select248_SW02 (N14530)
     MUXF5:I0->O           2   0.360   1.072  select1/select248_SW0_f5 (N13802)
     LUT4:I1->O            1   0.551   0.000  select1/select2482 (N14532)
     MUXF5:I0->O           2   0.360   1.216  select1/select248_f5 (select1/select2_map4289)
     LUT4:I0->O            9   0.551   1.463  ram/_and0000_inv1 (ram/_and0000_inv)
     LUT4:I0->O           16   0.551   1.576  N187LogicTrst141 (N190)
     LUT3:I0->O            1   0.551   0.801  N187LogicTrst1211 (data_7_IOBUF)
     IOBUF:I->IO               5.644          data_7_IOBUF (data<7>)
    ----------------------------------------
    Total                     17.126ns (9.752ns logic, 7.374ns route)
                                       (56.9% logic, 43.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
  Total number of paths / destination ports: 840 / 8
-------------------------------------------------------------------------
Offset:              18.117ns (Levels of Logic = 9)
  Source:            select1/selecta/mask_1 (LATCH)
  Destination:       data<6> (PAD)
  Source Clock:      select1/selecta/_and0000 falling

  Data Path: select1/selecta/mask_1 to data<6>
d910 10
a919 10
     LDCE:G->Q             7   0.633   1.405  select1/selecta/mask_1 (select1/selecta/mask_1)
     LUT4:I0->O            1   0.551   0.000  _and0000_inv181 (N14508)
     MUXF5:I1->O           1   0.360   1.140  _and0000_inv18_f5 (_and0000_inv_map4593)
     LUT4:I0->O            1   0.551   1.140  _and0000_inv108 (_and0000_inv_map4620)
     LUT4:I0->O            9   0.551   1.319  _and0000_inv211 (_and0000_inv)
     LUT4:I1->O            1   0.551   0.869  N199LogicTrst65 (N199LogicTrst_map4415)
     LUT3:I2->O            1   0.551   1.140  N199LogicTrst99_SW0 (N14163)
     LUT4:I0->O            1   0.551   0.000  N199LogicTrst1111 (N14501)
     MUXF5:I0->O           1   0.360   0.801  N199LogicTrst111_f5 (data_1_IOBUF)
     IOBUF:I->IO               5.644          data_1_IOBUF (data<1>)
d921 2
a922 2
    Total                     18.117ns (10.303ns logic, 7.814ns route)
                                       (56.9% logic, 43.1% route)
d925 2
a926 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
  Total number of paths / destination ports: 648 / 8
d928 2
a929 2
Offset:              18.861ns (Levels of Logic = 8)
  Source:            select1/selectc/mask_1 (LATCH)
d931 1
a931 1
  Source Clock:      select1/selectc/_and0000 falling
d933 1
a933 1
  Data Path: select1/selectc/mask_1 to data<7>
d937 8
a944 9
     LDCE:G->Q             7   0.633   1.405  select1/selectc/mask_1 (select1/selectc/mask_1)
     LUT4:I0->O            1   0.551   0.000  select1/selectc/selectout791 (N14518)
     MUXF5:I1->O           1   0.360   1.140  select1/selectc/selectout79_f5 (select1/selectc/selectout_map4980)
     LUT4_D:I0->O          3   0.551   0.975  select1/selectc/selectout169 (select1/selectc/selectout_map5007)
     LUT4:I2->O           25   0.551   2.152  intc/_not0027_SW0 (intc/_and0001)
     LUT2:I0->O            1   0.551   0.869  intc/_or0000_inv1 (intc/_or0000_inv)
     LUT4:I2->O           16   0.551   1.576  N187LogicTrst141 (N190)
     LUT3:I0->O            1   0.551   0.801  N187LogicTrst1211 (data_7_IOBUF)
     IOBUF:I->IO               5.644          data_7_IOBUF (data<7>)
d946 2
a947 2
    Total                     18.861ns (9.943ns logic, 8.918ns route)
                                       (52.7% logic, 47.3% route)
d950 2
a951 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectd/_and0000'
  Total number of paths / destination ports: 459 / 8
d953 2
a954 2
Offset:              18.964ns (Levels of Logic = 9)
  Source:            select1/selectd/mask_1 (LATCH)
d956 1
a956 28
  Source Clock:      select1/selectd/_and0000 falling

  Data Path: select1/selectd/mask_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             7   0.633   1.405  select1/selectd/mask_1 (select1/selectd/mask_1)
     LUT4:I0->O            1   0.551   0.000  select1/selectd/selectout791 (N14485)
     MUXF5:I1->O           1   0.360   1.140  select1/selectd/selectout79_f5 (select1/selectd/selectout_map4243)
     LUT4:I0->O            3   0.551   0.975  select1/selectd/selectout169 (select1/selectd/selectout_map4270)
     LUT3:I2->O           12   0.551   1.144  select1/selectd/selectout183 (trmsel)
     LUT4:I3->O            1   0.551   0.996  N187LogicTrst69 (N187LogicTrst_map4691)
     LUT3:I1->O            1   0.551   1.140  N187LogicTrst109_SW0 (N14179)
     LUT4:I0->O            1   0.551   0.869  N187LogicTrst109 (N187LogicTrst_map4696)
     LUT3:I2->O            1   0.551   0.801  N187LogicTrst1211 (data_7_IOBUF)
     IOBUF:I->IO               5.644          data_7_IOBUF (data<7>)
    ----------------------------------------
    Total                     18.964ns (10.494ns logic, 8.470ns route)
                                       (55.3% logic, 44.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset_n'
  Total number of paths / destination ports: 32 / 8
-------------------------------------------------------------------------
Offset:              14.894ns (Levels of Logic = 7)
  Source:            select1/selectb/datai_6 (LATCH)
  Destination:       data<6> (PAD)
  Source Clock:      reset_n falling
d958 1
a958 1
  Data Path: select1/selectb/datai_6 to data<6>
d962 10
a971 8
     LDE_1:G->Q            1   0.633   0.996  select1/selectb/datai_6 (select1/selectb/datai_6)
     LUT3:I1->O            1   0.551   0.869  N189LogicTrst15 (N189LogicTrst_map4564)
     LUT4:I2->O            1   0.551   0.827  N189LogicTrst47 (N189LogicTrst_map4572)
     LUT4:I3->O            1   0.551   0.869  N189LogicTrst80 (N189LogicTrst_map4578)
     LUT3:I2->O            1   0.551   1.140  N189LogicTrst114_SW0 (N14175)
     LUT4:I0->O            1   0.551   0.000  N189LogicTrst1261 (N14507)
     MUXF5:I0->O           1   0.360   0.801  N189LogicTrst126_f5 (data_6_IOBUF)
     IOBUF:I->IO               5.644          data_6_IOBUF (data<6>)
d973 2
a974 2
    Total                     14.894ns (9.392ns logic, 5.502ns route)
                                       (63.1% logic, 36.9% route)
d977 1
a977 1
CPU : 257.34 / 257.59 s | Elapsed : 258.00 / 258.00 s
d981 1
a981 1
Total memory usage is 232272 kilobytes
d984 2
a985 2
Number of warnings :  167 (   0 filtered)
Number of infos    :   10 (   0 filtered)
@


1.1.1.4
log
@8080 CPU project
@
text
@d4 1
a4 1
CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
d7 1
a7 1
CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
a100 2
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd" in Library work.
Architecture arch of Entity ps2_kbd is up to date.
d107 1
a108 3
Module <scnrom> compiled
Compiling verilog file "cpu8080.v" in library work
Module <scnromu> compiled
d116 1
a116 1
Compiling verilog include file "test.rom"
a145 7
Analyzing hierarchy for entity <ps2_kbd> in library <work> (architecture <arch>) with generics.
	FREQ = 50000

Analyzing hierarchy for module <scnrom> in library <work>.

Analyzing hierarchy for module <scnromu> in library <work>.

d147 1
a147 1
	CLK_DIV = 2
d149 1
a149 1
	FREQ = 50000
a206 1
	PIXEL_WIDTH = 1
d208 1
a208 1
	CLK_DIV = 2
d210 1
a210 1
	FREQ = 50000
d213 1
d217 3
a221 3
	WIDTH = 4
	PERIOD = 32
	START = 26
a234 10
Analyzing generic Entity <ps2_kbd> in library <work> (Architecture <arch>).
	FREQ = 50000
Entity <ps2_kbd> analyzed. Unit <ps2_kbd> generated.

Analyzing module <scnrom> in library <work>.
Module <scnrom> is correct for synthesis.
 
Analyzing module <scnromu> in library <work>.
Module <scnromu> is correct for synthesis.
 
d241 1
d323 1
a323 1
    Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 291.
d335 7
a341 7
    Found 5-bit adder for signal <$add0001> created at line 1514.
    Found 8-bit adder carry out for signal <$addsub0000> created at line 1507.
    Found 4-bit adder carry out for signal <$addsub0001> created at line 1508.
    Found 6-bit subtractor for signal <$sub0000> created at line 1520.
    Found 6-bit subtractor for signal <$sub0001> created at line 1526.
    Found 9-bit subtractor for signal <$sub0002> created at line 1519.
    Found 8-bit xor2 for signal <$xor0000> created at line 1537.
a349 27
Synthesizing Unit <ps2_kbd>.
    Related source file is "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd".
WARNING:Xst:646 - Signal <keyrel_r> is assigned but never used.
    Found 13-bit adder for signal <$addsub0000> created at line 112.
    Found 4-bit up counter for signal <bitcnt_r>.
    Found 1-bit register for signal <error_r>.
    Found 5-bit register for signal <ps2_clk_r>.
    Found 1-bit register for signal <rdy_r>.
    Found 10-bit register for signal <sc_r>.
    Found 13-bit register for signal <timer_r>.
    Summary:
	inferred   1 Counter(s).
	inferred  30 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <ps2_kbd> synthesized.


Synthesizing Unit <scnrom>.
    Related source file is "vgachr.v".
Unit <scnrom> synthesized.


Synthesizing Unit <scnromu>.
    Related source file is "vgachr.v".
Unit <scnromu> synthesized.


d360 1
a360 1
    Found 16-bit adder for signal <$addsub0000> created at line 398.
d366 1
a366 1
	inferred   3 D-type flip-flop(s).
d373 1
a373 1
    Found 16-bit adder for signal <$addsub0000> created at line 398.
d379 1
a379 1
	inferred   3 D-type flip-flop(s).
a399 1
INFO:Xst:1799 - State 0XXXXX is never reached in FSM <state>.
d402 3
a404 3
    | States             | 34                                             |
    | Transitions        | 901                                            |
    | Inputs             | 139                                            |
d409 1
a409 1
    | Reset State        | 000001                                         |
d413 1
a413 1
    Found 4x1-bit ROM for signal <$mux0043> created at line 309.
d421 9
a429 9
    Found 32-bit adder for signal <$add0001> created at line 491.
    Found 32-bit adder for signal <$add0002> created at line 503.
    Found 32-bit adder for signal <$add0003> created at line 515.
    Found 16-bit adder for signal <$add0004> created at line 975.
    Found 16-bit adder for signal <$add0005> created at line 886.
    Found 32-bit adder for signal <$add0006> created at line 560.
    Found 32-bit adder for signal <$add0007> created at line 548.
    Found 32-bit adder for signal <$add0008> created at line 536.
    Found 17-bit adder for signal <$add0009> created at line 481.
d437 11
a447 12
    Found 16-bit adder for signal <$addsub0007> created at line 1046.
    Found 6-bit adder for signal <$addsub0008>.
    Found 16-bit adder for signal <$addsub0009> created at line 1087.
    Found 8-bit adder carry out for signal <$addsub0010>.
    Found 4-bit adder carry out for signal <$addsub0011> created at line 356.
    Found 8-bit adder carry out for signal <$addsub0012>.
    Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 353.
    Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1324.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0022> created at line 309.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0023> created at line 309.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 309.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 309.
d449 1
a449 1
    Found 3-bit 4-to-1 multiplexer for signal <$mux0050> created at line 313.
d451 7
a457 6
    Found 16-bit adder for signal <$share0000> created at line 309.
    Found 16-bit addsub for signal <$share0006> created at line 309.
    Found 32-bit subtractor for signal <$sub0000> created at line 536.
    Found 32-bit subtractor for signal <$sub0001> created at line 548.
    Found 32-bit subtractor for signal <$sub0002> created at line 560.
    Found 16-bit subtractor for signal <$sub0003> created at line 757.
d547 1
a547 1
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <fchsta> of Case statement line 654 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
d554 2
a555 2
    | Transitions        | 7                                              |
    | Inputs             | 1                                              |
d558 2
a559 2
    | Clock enable       | $not0008 (positive)                            |
    | Reset              | rst (positive)                                 |
d565 1
a565 1
WARNING:Xst:643 - "vgachr.v" line 706: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
d567 8
a574 10
    Found 11-bit adder for signal <$add0000> created at line 699.
    Found 9-bit subtractor for signal <$addsub0000> created at line 706.
    Found 11-bit adder for signal <$addsub0001> created at line 706.
    Found 11-bit comparator equal for signal <$cmp_eq0003> created at line 662.
    Found 7-bit comparator greatequal for signal <$cmp_ge0000> created at line 635.
    Found 5-bit comparator greatequal for signal <$cmp_ge0001> created at line 639.
    Found 7-bit comparator less for signal <$cmp_lt0000> created at line 635.
    Found 5-bit comparator less for signal <$cmp_lt0001> created at line 639.
    Found 8-bit comparator less for signal <$cmp_lt0002> created at line 706.
    Found 9x6-bit multiplier for signal <$mult0002> created at line 706.
a575 1
    Found 8-bit register for signal <curchr>.
a576 1
    Found 8-bit register for signal <pixdatl>.
d585 1
a585 1
	inferred  32 D-type flip-flop(s).
d588 1
a588 1
	inferred   6 Comparator(s).
a594 6
WARNING:Xst:646 - Signal <parity> is assigned but never used.
WARNING:Xst:646 - Signal <error> is assigned but never used.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state> of Case statement line 296 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <state> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
d597 6
a602 5
    | States             | 16                                             |
    | Transitions        | 60                                             |
    | Inputs             | 18                                             |
    | Outputs            | 15                                             |
    | Clock              | clock (rising_edge)                            |
d605 1
a605 1
    | Reset State        | 0100                                           |
a608 2
    Found 4x11-bit ROM for signal <$mux0014> created at line 296.
    Found 4x1-bit ROM for signal <$mux0015> created at line 296.
d610 4
a613 20
    Found 11-bit adder for signal <$add0002> created at line 470.
    Found 11-bit adder for signal <$addsub0000> created at line 434.
    Found 11-bit adder for signal <$addsub0001>.
    Found 11-bit adder carry out for signal <$addsub0002> created at line 453.
    Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 308.
    Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 335.
    Found 8-bit comparator greatequal for signal <$cmp_ge0002> created at line 283.
    Found 8-bit comparator greatequal for signal <$cmp_ge0003> created at line 285.
    Found 12-bit comparator greater for signal <$cmp_gt0000> created at line 453.
    Found 11-bit comparator greater for signal <$cmp_gt0001> created at line 347.
    Found 12-bit comparator greater for signal <$cmp_gt0002> created at line 453.
    Found 8-bit comparator lessequal for signal <$cmp_le0000> created at line 283.
    Found 8-bit comparator lessequal for signal <$cmp_le0001> created at line 285.
    Found 11-bit comparator less for signal <$cmp_lt0000> created at line 320.
    Found 11-bit comparator less for signal <$cmp_lt0001> created at line 432.
    Found 11-bit comparator less for signal <$cmp_lt0002> created at line 467.
    Found 11-bit comparator less for signal <$cmp_lt0003> created at line 512.
    Found 11-bit comparator less for signal <$cmp_lt0004> created at line 354.
    Found 11-bit addsub for signal <$share0000> created at line 296.
    Found 1-bit register for signal <capslock>.
a614 1
    Found 1-bit register for signal <clrrdy>.
a618 1
    Found 1-bit register for signal <cmread>.
a621 3
    Found 1-bit register for signal <extcod>.
    Found 1-bit register for signal <leftctrl>.
    Found 1-bit register for signal <leftshift>.
a622 5
    Found 1-bit register for signal <relcod>.
    Found 1-bit register for signal <rightctrl>.
    Found 1-bit register for signal <rightshift>.
    Found 1-bit register for signal <scnrdy>.
    Found 11-bit register for signal <tcursor>.
d626 3
a628 4
	inferred   2 ROM(s).
	inferred  71 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred  14 Comparator(s).
d635 3
d646 1
a646 1
# RAMs                                                 : 3
d649 1
a649 2
 1920x8-bit single-port block RAM                      : 1
# ROMs                                                 : 5
d652 1
a652 2
 4x1-bit ROM                                           : 2
 4x11-bit ROM                                          : 1
d655 2
a656 5
# Adders/Subtractors                                   : 53
 11-bit adder                                          : 5
 11-bit adder carry out                                : 1
 11-bit addsub                                         : 1
 13-bit adder                                          : 1
a672 1
 4-bit up counter                                      : 1
d675 1
a675 1
 8-bit up counter                                      : 1
d678 3
a680 5
# Registers                                            : 99
 1-bit register                                        : 49
 10-bit register                                       : 1
 11-bit register                                       : 3
 13-bit register                                       : 1
a684 1
 5-bit register                                        : 1
d686 1
a686 1
 8-bit register                                        : 27
d691 2
a692 6
# Comparators                                          : 27
 11-bit comparator equal                               : 1
 11-bit comparator greatequal                          : 1
 11-bit comparator greater                             : 1
 11-bit comparator less                                : 5
 12-bit comparator greater                             : 2
d700 1
a700 1
 8-bit comparator greatequal                           : 3
a701 1
 8-bit comparator lessequal                            : 2
d708 3
a710 2
# Tristates                                            : 12
 8-bit tristate buffer                                 : 12
d722 12
a733 21
Optimizing FSM <adm3a/state> on signal <state[1:16]> with speed1 encoding.
---------------------------
 State | Encoding
---------------------------
 0000  | 0000100000000000
 0001  | 0100000000000000
 0010  | 0000010000000000
 0011  | 0000001000000000
 0100  | 1000000000000000
 0101  | 0000000100000000
 0110  | 0000000010000000
 0111  | 0000000001000000
 1000  | 0001000000000000
 1001  | 0010000000000000
 1010  | 0000000000100000
 1011  | 0000000000001000
 1100  | 0000000000000100
 1101  | 0000000000000010
 1110  | 0000000000010000
 1111  | 0000000000000001
---------------------------
d745 36
a780 40
Optimizing FSM <cpu/state> on signal <state[1:36]> with speed1 encoding.
------------------------------------------------
 State  | Encoding
------------------------------------------------
 000001 | 000001000000000000000000000000000000
 000010 | 000000100000000000000000000000000000
 000011 | 100000000000000000000000000000000000
 000100 | 000100000000000000000000000000000000
 000101 | 000000000001000000000000000000000000
 000110 | 010000000000100000000000000000000000
 000111 | 010000001000000000000000000000000000
 001000 | 010000000000000001000000000000000000
 001001 | 010000000000000000010000000000000000
 001010 | 010000000000000000000100000000000000
 001011 | 010000000000000000000010000000000000
 001100 | 000010000000000000001000000000000000
 001101 | 010000000000000000000000000100000000
 001110 | 000000000100000000000000000000000000
 001111 | 000000000000010000000000000000000000
 010000 | 000000000000001000000000000000000000
 010001 | 000010000000000100000000000000000000
 010010 | 000000000010000000000000000000000000
 010011 | 000000000000000000000000000000000100
 010100 | 001010000000000000000000000000000000
 010101 | 010000000000000000000001000000000000
 010110 | 000000000000000000000000000001000000
 010111 | 000000000000000000000000000000000001
 011000 | 010000000000000000000000000010000000
 011001 | 000000000000000000000000000000010000
 011010 | 000000000000000000000000000000100000
 011011 | 000000000000000000000000000000001000
 011100 | 010000000000000000000000000000000010
 011101 | 000010000000000010000000000000000000
 011110 | 000010000000000000000000100000000000
 011111 | 000010000000000000000000001000000000
 0XXXXX | unreached
 100000 | 000010000000000000100000000000000000
 100001 | 000000000000000000000000010000000000
 100010 | 010000010000000000000000000000000000
------------------------------------------------
a790 1
WARNING:Xst:2404 -  FFs/Latches <curchr<7:7>> (without init value) have a constant value of 0 in block <chrmemmap>.
d794 1
d799 8
a806 1
INFO:Xst:2261 - The FF/Latch <rgb_r_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <rgb_r_1> <rgb_r_2> <rgb_r_3> <rgb_r_4> <rgb_r_5> <rgb_r_6> <rgb_r_7> <rgb_r_8> 
d814 1
a814 1
# RAMs                                                 : 4
d818 1
a818 2
 1920x8-bit single-port block RAM                      : 1
# ROMs                                                 : 4
d820 1
a820 2
 4x1-bit ROM                                           : 2
 4x11-bit ROM                                          : 1
d823 2
a824 5
# Adders/Subtractors                                   : 53
 11-bit adder                                          : 5
 11-bit adder carry out                                : 1
 11-bit addsub                                         : 1
 13-bit adder                                          : 1
a840 1
 4-bit up counter                                      : 1
d843 1
a843 1
 8-bit up counter                                      : 1
d846 2
a847 2
# Registers                                            : 552
 Flip-Flops                                            : 552
d851 2
a852 6
# Comparators                                          : 27
 11-bit comparator equal                               : 1
 11-bit comparator greatequal                          : 1
 11-bit comparator greater                             : 1
 11-bit comparator less                                : 5
 12-bit comparator greater                             : 2
d860 1
a860 1
 8-bit comparator greatequal                           : 3
a861 1
 8-bit comparator lessequal                            : 2
d877 2
a878 3
WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0000>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_7> are dual, second instance is removed
WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_6> and unit <LPM_COMPARE_8> are dual, second instance is removed
WARNING:Xst:1989 - Unit <terminal>: instances <Mcompar__cmp_gt0000>, <Mcompar__cmp_gt0002> of unit <LPM_COMPARE_12> are equivalent, second instance is removed
d1004 5
a1008 1
WARNING:Xst:1710 - FF/Latch  <scnadr_0> (without init value) has a constant value of 0 in block <chrmemmap>.
d1012 5
a1016 1
WARNING:Xst:2040 - Unit testbench: 16 multi-source signals are replaced by logic (pull-up yes): adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N185, N187, N189, N1911, N193, N195, N197, N199.
a1020 4
Optimizing unit <alu> ...

Optimizing unit <ps2_kbd> ...

d1027 2
d1030 1
d1033 1
a1033 1
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 32.
d1038 7
a1044 9
FlipFlop adm3a/display/chrcnt_0 has been replicated 1 time(s)
FlipFlop adm3a/display/chrcnt_1 has been replicated 1 time(s)
FlipFlop adm3a/display/chrcnt_2 has been replicated 1 time(s)
FlipFlop adm3a/display/chrcnt_3 has been replicated 1 time(s)
FlipFlop adm3a/vgai/sc_r_0 has been replicated 1 time(s)
FlipFlop adm3a/vgai/sc_r_3 has been replicated 1 time(s)
FlipFlop cpu/addr_0 has been replicated 1 time(s)
FlipFlop cpu/addr_1 has been replicated 1 time(s)
FlipFlop cpu/addr_2 has been replicated 2 time(s)
a1049 4
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/state_FFd13> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <cpu/state_FFd1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <adm3a/vgai/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/vgai/ps2_clk_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
d1058 2
a1059 2
# Registers                                            : 606
 Flip-Flops                                            : 606
d1085 1
a1085 1
# IOs                              : 54
d1088 1
a1088 1
# BELS                             : 6230
d1090 11
a1100 11
#      INV                         : 100
#      LUT1                        : 198
#      LUT2                        : 370
#      LUT2_D                      : 38
#      LUT2_L                      : 6
#      LUT3                        : 1142
#      LUT3_D                      : 30
#      LUT3_L                      : 24
#      LUT4                        : 2193
#      LUT4_D                      : 77
#      LUT4_L                      : 238
d1102 4
a1105 4
#      MUXCY                       : 619
#      MUXF5                       : 588
#      MUXF6                       : 178
#      MUXF7                       : 62
d1108 15
a1122 15
#      XORCY                       : 314
# FlipFlops/Latches                : 694
#      FD                          : 7
#      FDC                         : 23
#      FDCE                        : 57
#      FDE                         : 311
#      FDE_1                       : 8
#      FDP                         : 6
#      FDPE                        : 21
#      FDR                         : 40
#      FDRE                        : 32
#      FDRE_1                      : 42
#      FDRS                        : 46
#      FDRSE                       : 9
#      FDS                         : 3
d1126 1
a1126 1
# RAMS                             : 843
d1128 3
a1130 2
#      RAMB16_S9                   : 3
# Clock Buffers                    : 2
d1132 2
a1133 2
# IO Buffers                       : 52
#      IBUF                        : 2
d1135 1
a1135 1
#      OBUF                        : 42
d1145 4
a1148 4
 Number of Slices:                    2302  out of   7680    29%  
 Number of Slice Flip Flops:           694  out of  15360     4%  
 Number of 4 input LUTs:              6096  out of  15360    39%  
    Number used as logic:             4416
d1150 3
a1152 3
 Number of IOs:                         54
 Number of bonded IOBs:                 54  out of    173    31%  
 Number of BRAMs:                        3  out of     24    12%  
d1154 1
a1154 1
 Number of GCLKs:                        2  out of      8    25%  
d1169 2
a1170 1
clock                                                | BUFGP                          | 1446  |
d1172 4
a1175 4
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/comp_4)| 14    |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_1)| 14    |
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/mask_5)| 14    |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/mask_1)| 14    |
d1184 5
a1188 5
-----------------------------------+-----------------------------------------------------+-------+
Control Signal                     | Buffer(FF name)                                     | Load  |
-----------------------------------+-----------------------------------------------------+-------+
reset(reset1_INV_0:O)              | NONE(adm3a/display/vgai/gen_syncs_fit.hsync/cnt_r_4)| 163   |
-----------------------------------+-----------------------------------------------------+-------+
d1194 4
a1197 4
   Minimum period: 21.036ns (Maximum Frequency: 47.538MHz)
   Minimum input arrival time before clock: 8.669ns
   Maximum output required time after clock: 19.931ns
   Maximum combinational path delay: 7.342ns
d1204 28
d1233 2
a1234 2
  Clock period: 21.036ns (frequency: 47.538MHz)
  Total number of paths / destination ports: 235247 / 9275
d1236 3
a1238 3
Delay:               10.518ns (Levels of Logic = 6)
  Source:            cpu/addr_10 (FF)
  Destination:       intc/active_7 (FF)
d1240 1
a1240 1
  Destination Clock: clock falling
d1242 1
a1242 1
  Data Path: cpu/addr_10 to intc/active_7
d1246 28
a1273 8
     FDE:C->Q              6   0.720   1.029  cpu/addr_10 (cpu/addr_10)
     LUT4:I3->O            1   0.551   0.000  select1/selectc/selectout1511 (N16663)
     MUXF5:I1->O           1   0.360   1.140  select1/selectc/selectout151_f5 (select1/selectc/selectout_map5945)
     LUT4_D:I0->O          9   0.551   1.150  select1/selectc/selectout169 (select1/selectc/selectout_map5947)
     LUT4:I3->O            1   0.551   0.869  intc/_not0027_SW0_1 (intc/_not0027_SW0)
     LUT4_D:I2->O          7   0.551   1.092  intc/_not00161 (N275)
     LUT4:I3->O            1   0.551   0.801  intc/_not00171 (intc/_not0017)
     FDRE_1:CE                 0.602          intc/active_6
d1275 27
a1301 2
    Total                     10.518ns (4.437ns logic, 6.081ns route)
                                       (42.2% logic, 57.8% route)
d1305 1
a1305 1
  Total number of paths / destination ports: 576 / 576
d1307 1
a1307 1
Offset:              8.669ns (Levels of Logic = 2)
d1309 1
a1309 1
  Destination:       cpu/readmem (FF)
d1312 1
a1312 1
  Data Path: reset_n to cpu/readmem
d1316 4
a1319 3
     BUFGP:I->O          234   0.401   3.010  reset_n_BUFGP (reset_n_BUFGP)
     INV:I->O            351   0.551   3.680  reset1_INV_0 (reset)
     FDRSE:R                   1.026          cpu/writemem
d1321 2
a1322 2
    Total                      8.669ns (1.978ns logic, 6.691ns route)
                                       (22.8% logic, 77.2% route)
d1337 1
a1337 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15204)
d1356 1
a1356 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15204)
d1375 1
a1375 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15204)
d1394 1
a1394 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15204)
d1401 2
a1402 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  Total number of paths / destination ports: 2401 / 47
d1404 1
a1404 1
Offset:              19.931ns (Levels of Logic = 9)
d1407 1
a1407 1
  Source Clock:      clock rising
d1414 1
a1414 1
     LUT4:I1->O            3   0.551   1.246  select1/selacc426 (select1/selacc4_map5253)
d1416 6
a1421 7
     LUT4:I0->O            9   0.551   1.124  select1/selecta/_and0001_inv1 (select1/selecta/_and0001_inv)
     MUXF5:S->O            1   0.621   0.869  N185LogicTrst116_f5 (N185LogicTrst1_map5594)
     LUT4:I2->O            1   0.551   0.000  N185LogicTrst142_SW01 (N16749)
     MUXF5:I1->O           1   0.360   1.140  N185LogicTrst142_SW0_f5 (N16357)
     LUT4:I0->O           16   0.551   1.576  N185LogicTrst142 (N2511)
     LUT3:I0->O            1   0.551   0.801  N197LogicTrst114 (data_1_IOBUF)
     IOBUF:I->IO               5.644          data_1_IOBUF (data<1>)
d1423 2
a1424 2
    Total                     19.931ns (10.651ns logic, 9.280ns route)
                                       (53.4% logic, 46.6% route)
d1427 2
a1428 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
  Total number of paths / destination ports: 648 / 8
d1430 2
a1431 2
Offset:              19.540ns (Levels of Logic = 9)
  Source:            select1/selectc/mask_1 (LATCH)
d1433 1
a1433 1
  Source Clock:      select1/selectc/_and0000 falling
d1435 1
a1435 1
  Data Path: select1/selectc/mask_1 to data<7>
d1439 6
a1444 10
     LDCE:G->Q             7   0.633   1.261  select1/selectc/mask_1 (select1/selectc/mask_1)
     LUT4:I1->O            1   0.551   0.000  select1/selectc/selectout1511 (N16663)
     MUXF5:I1->O           1   0.360   1.140  select1/selectc/selectout151_f5 (select1/selectc/selectout_map5945)
     LUT4_D:I0->O          9   0.551   1.150  select1/selectc/selectout169 (select1/selectc/selectout_map5947)
     LUT4_D:I3->O         28   0.551   2.169  intc/_not0027_SW0 (intc/_and0009)
     LUT4:I0->O            1   0.551   0.000  N185LogicTrst142_SW01 (N16749)
     MUXF5:I1->O           1   0.360   1.140  N185LogicTrst142_SW0_f5 (N16357)
     LUT4:I0->O           16   0.551   1.576  N185LogicTrst142 (N2511)
     LUT3:I0->O            1   0.551   0.801  N197LogicTrst114 (data_1_IOBUF)
     IOBUF:I->IO               5.644          data_1_IOBUF (data<1>)
d1446 2
a1447 2
    Total                     19.540ns (10.303ns logic, 9.237ns route)
                                       (52.7% logic, 47.3% route)
d1453 1
a1453 1
Offset:              19.033ns (Levels of Logic = 10)
d1463 8
a1470 10
     LUT4:I0->O            1   0.551   0.000  select1/select248_SW02 (N16686)
     MUXF5:I0->O           2   0.360   1.072  select1/select248_SW0_f5 (N15841)
     LUT4:I1->O            1   0.551   0.000  select1/select2482 (N16688)
     MUXF5:I0->O           2   0.360   1.216  select1/select248_f5 (select1/select2_map5401)
     LUT4:I0->O            9   0.551   1.319  ram/_and0000_inv1 (ram/_and0000_inv)
     LUT4:I1->O            1   0.551   0.000  N185LogicTrst142_SW01 (N16749)
     MUXF5:I1->O           1   0.360   1.140  N185LogicTrst142_SW0_f5 (N16357)
     LUT4:I0->O           16   0.551   1.576  N185LogicTrst142 (N2511)
     LUT3:I0->O            1   0.551   0.801  N197LogicTrst114 (data_1_IOBUF)
     IOBUF:I->IO               5.644          data_1_IOBUF (data<1>)
d1472 2
a1473 2
    Total                     19.033ns (10.663ns logic, 8.370ns route)
                                       (56.0% logic, 44.0% route)
d1479 1
a1479 1
Offset:              18.339ns (Levels of Logic = 8)
d1481 1
a1481 1
  Destination:       data<7> (PAD)
d1484 1
a1484 1
  Data Path: select1/selecta/mask_1 to data<7>
d1489 8
a1496 7
     LUT4:I0->O            1   0.551   0.000  _and0000_inv181 (N16644)
     MUXF5:I1->O           1   0.360   1.140  _and0000_inv18_f5 (_and0000_inv_map5463)
     LUT4:I0->O            1   0.551   1.140  _and0000_inv108 (_and0000_inv_map5490)
     LUT4:I0->O            9   0.551   1.124  _and0000_inv211 (_and0000_inv)
     MUXF5:S->O            1   0.621   1.140  N185LogicTrst142_SW0_f5 (N16357)
     LUT4:I0->O           16   0.551   1.576  N185LogicTrst142 (N2511)
     LUT3:I0->O            1   0.551   0.801  N197LogicTrst114 (data_1_IOBUF)
d1499 2
a1500 2
    Total                     18.339ns (10.013ns logic, 8.326ns route)
                                       (54.6% logic, 45.4% route)
d1503 2
a1504 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectd/_and0000'
  Total number of paths / destination ports: 624 / 8
d1506 2
a1507 2
Offset:              17.613ns (Levels of Logic = 8)
  Source:            select1/selectd/mask_1 (LATCH)
d1509 1
a1509 1
  Source Clock:      select1/selectd/_and0000 falling
d1511 1
a1511 1
  Data Path: select1/selectd/mask_1 to data<7>
d1515 8
a1522 8
     LDCE:G->Q             7   0.633   1.261  select1/selectd/mask_1 (select1/selectd/mask_1)
     LUT4:I1->O            1   0.551   0.000  select1/selectd/selectout791 (N16624)
     MUXF5:I1->O           1   0.360   1.140  select1/selectd/selectout79_f5 (select1/selectd/selectout_map5291)
     LUT4_D:I0->O          9   0.551   1.319  select1/selectd/selectout169 (select1/selectd/selectout_map5318)
     LUT4:I1->O            1   0.551   1.140  N185LogicTrst1231_SW0_SW0 (N16367)
     LUT4:I0->O            1   0.551   1.140  N185LogicTrst1231_SW0 (N16227)
     LUT4:I0->O            1   0.551   0.869  N185LogicTrst1231 (N185LogicTrst_map5739)
     LUT3:I2->O            1   0.551   0.801  N185LogicTrst1291 (data_7_IOBUF)
d1525 2
a1526 2
    Total                     17.613ns (9.943ns logic, 7.670ns route)
                                       (56.5% logic, 43.5% route)
d1529 2
a1530 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset_n'
  Total number of paths / destination ports: 32 / 8
d1532 4
a1535 4
Offset:              16.225ns (Levels of Logic = 7)
  Source:            select1/selectb/datai_3 (LATCH)
  Destination:       data<3> (PAD)
  Source Clock:      reset_n falling
d1537 1
a1537 1
  Data Path: select1/selectb/datai_3 to data<3>
d1541 10
a1550 8
     LDE_1:G->Q            1   0.633   0.869  select1/selectb/datai_3 (select1/selectb/datai_3)
     LUT4:I2->O            1   0.551   0.996  N193LogicTrst26 (N193LogicTrst_map5610)
     LUT4:I1->O            1   0.551   0.827  N193LogicTrst34 (N193LogicTrst_map5612)
     LUT4:I3->O            1   0.551   1.140  N193LogicTrst61 (N193LogicTrst_map5618)
     LUT4:I0->O            1   0.551   1.140  N193LogicTrst97_SW0 (N16219)
     LUT4:I0->O            1   0.551   0.869  N193LogicTrst97 (N193LogicTrst_map5625)
     LUT3:I2->O            1   0.551   0.801  N193LogicTrst110 (data_3_IOBUF)
     IOBUF:I->IO               5.644          data_3_IOBUF (data<3>)
d1552 2
a1553 2
    Total                     16.225ns (9.583ns logic, 6.642ns route)
                                       (59.1% logic, 40.9% route)
d1556 2
a1557 2
Timing constraint: Default path analysis
  Total number of paths / destination ports: 2 / 2
d1559 4
a1562 3
Delay:               7.342ns (Levels of Logic = 2)
  Source:            ps2_data (PAD)
  Destination:       diag<4> (PAD)
d1564 1
a1564 1
  Data Path: ps2_data to diag<4>
d1568 8
a1575 2
     IBUF:I->O             2   0.821   0.877  ps2_data_IBUF (ps2_data_IBUF)
     OBUF:I->O                 5.644          diag_4_OBUF (diag<4>)
d1577 2
a1578 2
    Total                      7.342ns (6.465ns logic, 0.877ns route)
                                       (88.1% logic, 11.9% route)
d1581 1
a1581 1
CPU : 254.56 / 254.84 s | Elapsed : 255.00 / 255.00 s
d1585 1
a1585 1
Total memory usage is 236048 kilobytes
d1588 2
a1589 2
Number of warnings :  155 (   0 filtered)
Number of infos    :   15 (   0 filtered)
@


1.1.1.5
log
@8080 CPU project
@
text
@d4 1
a4 1
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
d7 1
a7 1
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
d104 2
a105 5
Package <vga_pckg> compiled.
Entity <vga> compiled.
Entity <vga> (Architecture <vga_arch>) compiled.
Entity <sync> compiled.
Entity <sync> (Architecture <sync_arch>) compiled.
d228 1
a229 1
	VISIBLE = 640
a563 1
WARNING:Xst:646 - Signal <curatr<4>> is assigned but never used.
d595 1
a595 21
    Found 1920x5-bit dual-port block RAM for signal <atrbuf>.
    -----------------------------------------------------------------------
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1920-word x 5-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <write>         | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <attr>          |          |
    |     doA            | connected to signal <attro>         |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 1920-word x 5-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk>           | rise     |
    |     addrB          | connected to internal node          |          |
    |     doB            | connected to signal <curatr>        |          |
    -----------------------------------------------------------------------
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <fchsta> of Case statement line 867 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
d613 1
a613 2
WARNING:Xst:643 - "vgachr.v" line 939: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit tristate buffer for signal <attr>.
d615 10
a624 24
    Found 11-bit adder for signal <$add0000> created at line 922.
    Found 9-bit subtractor for signal <$addsub0000> created at line 939.
    Found 11-bit adder for signal <$addsub0001> created at line 939.
    Found 11-bit comparator equal for signal <$cmp_eq0003> created at line 876.
    Found 32-bit comparator greatequal for signal <$cmp_ge0000> created at line 808.
    Found 7-bit comparator greatequal for signal <$cmp_ge0001> created at line 848.
    Found 5-bit comparator greatequal for signal <$cmp_ge0002> created at line 852.
    Found 7-bit comparator less for signal <$cmp_lt0000> created at line 848.
    Found 5-bit comparator less for signal <$cmp_lt0001> created at line 852.
    Found 8-bit comparator less for signal <$cmp_lt0002> created at line 939.
    Found 9x6-bit multiplier for signal <$mult0002> created at line 939.
    Found 16-bit 4-to-1 multiplexer for signal <$mux0000> created at line 905.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0001> created at line 898.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0002> created at line 898.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0003> created at line 898.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0004> created at line 898.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 898.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0006> created at line 898.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0007> created at line 898.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0008> created at line 898.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0009> created at line 877.
    Found 1-bit xor2 for signal <$xor0000> created at line 897.
    Found 32-bit up counter for signal <blinkcnt>.
    Found 1-bit register for signal <blon>.
d634 2
a635 2
	inferred   3 RAM(s).
	inferred   4 Counter(s).
d637 1
a637 1
	inferred  33 D-type flip-flop(s).
d640 2
a641 3
	inferred   7 Comparator(s).
	inferred  32 Multiplexer(s).
	inferred  13 Tristate(s).
a647 1
WARNING:Xst:646 - Signal <cmattri<7:5>> is assigned but never used.
d649 4
a652 1
    Register <cmattre> equivalent to <cmdatae> has been removed
d655 4
a658 4
    | States             | 20                                             |
    | Transitions        | 88                                             |
    | Inputs             | 21                                             |
    | Outputs            | 21                                             |
d662 1
a662 1
    | Reset State        | 00100                                          |
d666 2
a667 2
WARNING:Xst:643 - "vgachr.v" line 682: The result of a 9x8-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 4x1-bit ROM for signal <$mux0023> created at line 366.
d669 19
a687 30
    Found 11-bit adder for signal <$add0002> created at line 552.
    Found 9-bit subtractor for signal <$addsub0000> created at line 682.
    Found 11-bit adder for signal <$addsub0001> created at line 515.
    Found 11-bit adder for signal <$addsub0002>.
    Found 11-bit adder carry out for signal <$addsub0003> created at line 535.
    Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 378.
    Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 407.
    Found 8-bit comparator greatequal for signal <$cmp_ge0002> created at line 679.
    Found 8-bit comparator greatequal for signal <$cmp_ge0003> created at line 352.
    Found 8-bit comparator greatequal for signal <$cmp_ge0004> created at line 355.
    Found 12-bit comparator greater for signal <$cmp_gt0000> created at line 535.
    Found 8-bit comparator greater for signal <$cmp_gt0001> created at line 701.
    Found 11-bit comparator greater for signal <$cmp_gt0002> created at line 419.
    Found 12-bit comparator greater for signal <$cmp_gt0003> created at line 535.
    Found 8-bit comparator lessequal for signal <$cmp_le0000> created at line 679.
    Found 8-bit comparator lessequal for signal <$cmp_le0001> created at line 679.
    Found 8-bit comparator lessequal for signal <$cmp_le0002> created at line 352.
    Found 8-bit comparator lessequal for signal <$cmp_le0003> created at line 355.
    Found 11-bit comparator less for signal <$cmp_lt0000> created at line 392.
    Found 11-bit comparator less for signal <$cmp_lt0001> created at line 513.
    Found 11-bit comparator less for signal <$cmp_lt0002> created at line 549.
    Found 11-bit comparator less for signal <$cmp_lt0003> created at line 597.
    Found 8-bit comparator less for signal <$cmp_lt0004> created at line 701.
    Found 11-bit comparator less for signal <$cmp_lt0005> created at line 426.
    Found 9x8-bit multiplier for signal <$mult0002> created at line 682.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
    Found 1-bit 8-to-1 multiplexer for signal <$mux0007>.
    Found 11-bit addsub for signal <$share0000> created at line 366.
    Found 10-bit subtractor for signal <$sub0000> created at line 682.
    Found 5-bit subtractor for signal <$sub0001> created at line 702.
a691 2
    Found 5-bit tristate buffer for signal <cmattr>.
    Found 8-bit register for signal <cmattri>.
a696 1
    Found 5-bit register for signal <curatr>.
a699 1
    Found 1-bit register for signal <extkey>.
a705 1
    Found 8-bit register for signal <rowchr>.
d711 5
a715 7
	inferred   1 ROM(s).
	inferred  93 D-type flip-flop(s).
	inferred   8 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred  19 Comparator(s).
	inferred   2 Multiplexer(s).
	inferred  21 Tristate(s).
d729 1
a729 1
# RAMs                                                 : 4
a730 1
 1920x5-bit dual-port block RAM                        : 1
d733 1
a733 1
# ROMs                                                 : 4
d737 2
a738 1
# Multipliers                                          : 2
d740 1
a740 3
 9x8-bit multiplier                                    : 1
# Adders/Subtractors                                   : 56
 10-bit subtractor                                     : 1
a752 1
 5-bit subtractor                                      : 1
d759 2
a760 3
 9-bit subtractor                                      : 4
# Counters                                             : 6
 32-bit up counter                                     : 1
d767 2
a768 2
# Registers                                            : 104
 1-bit register                                        : 51
d776 1
a776 1
 5-bit register                                        : 2
d778 1
a778 1
 8-bit register                                        : 29
d783 1
a783 1
# Comparators                                          : 33
a788 1
 32-bit comparator greatequal                          : 1
d796 6
a801 8
 8-bit comparator greatequal                           : 4
 8-bit comparator greater                              : 1
 8-bit comparator less                                 : 2
 8-bit comparator lessequal                            : 4
# Multiplexers                                         : 32
 1-bit 4-to-1 multiplexer                              : 17
 1-bit 8-to-1 multiplexer                              : 3
 16-bit 4-to-1 multiplexer                             : 1
d803 1
a803 1
 8-bit 4-to-1 multiplexer                              : 4
d805 1
a805 2
# Tristates                                            : 14
 5-bit tristate buffer                                 : 2
d807 1
a807 2
# Xors                                                 : 3
 1-bit xor2                                            : 1
d818 2
a819 2
Optimizing FSM <adm3a/state> on signal <state[1:20]> with one-hot encoding.
-------------------------------
d821 18
a838 22
-------------------------------
 00000 | 00000000000000100000
 00001 | 00000000000000000010
 00010 | 00000000000001000000
 00011 | 00000000000010000000
 00100 | 00000000000000000001
 00101 | 00000000000100000000
 00110 | 00000000001000000000
 00111 | 00000000010000000000
 01000 | 00000000000000001000
 01001 | 00000000000000000100
 01010 | 00000000100000000000
 01011 | 00000010000000000000
 01100 | 00000100000000000000
 01101 | 00001000000000000000
 01110 | 00000001000000000000
 01111 | 00010000000000000000
 10000 | 00000000000000010000
 10001 | 00100000000000000000
 10010 | 10000000000000000000
 10011 | 01000000000000000000
-------------------------------
a901 1
WARNING:Xst:2404 -  FFs/Latches <rowchr<7:7>> (without init value) have a constant value of 0 in block <terminal>.
a908 3
WARNING:Xst:1291 - FF/Latch <cmattri_5> is unconnected in block <terminal>.
WARNING:Xst:1291 - FF/Latch <cmattri_6> is unconnected in block <terminal>.
WARNING:Xst:1291 - FF/Latch <cmattri_7> is unconnected in block <terminal>.
d916 1
a916 1
# RAMs                                                 : 5
a918 1
 1920x5-bit dual-port block RAM                        : 1
d921 1
a921 1
# ROMs                                                 : 3
d924 2
a925 1
# Multipliers                                          : 2
d927 1
a927 3
 9x8-bit multiplier                                    : 1
# Adders/Subtractors                                   : 56
 10-bit subtractor                                     : 1
a939 1
 5-bit subtractor                                      : 1
d946 2
a947 3
 9-bit subtractor                                      : 4
# Counters                                             : 6
 32-bit up counter                                     : 1
d954 2
a955 2
# Registers                                            : 575
 Flip-Flops                                            : 575
d959 1
a959 1
# Comparators                                          : 33
a964 1
 32-bit comparator greatequal                          : 1
d972 6
a977 8
 8-bit comparator greatequal                           : 4
 8-bit comparator greater                              : 1
 8-bit comparator less                                 : 2
 8-bit comparator lessequal                            : 4
# Multiplexers                                         : 32
 1-bit 4-to-1 multiplexer                              : 17
 1-bit 8-to-1 multiplexer                              : 3
 16-bit 4-to-1 multiplexer                             : 1
d979 1
a979 1
 8-bit 4-to-1 multiplexer                              : 4
d981 1
a981 2
# Xors                                                 : 3
 1-bit xor2                                            : 1
d990 3
a992 3
WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_7> are dual, second instance is removed
WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0002>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_6> and unit <LPM_COMPARE_8> are dual, second instance is removed
WARNING:Xst:1989 - Unit <terminal>: instances <Mcompar__cmp_gt0000>, <Mcompar__cmp_gt0003> of unit <LPM_COMPARE_13> are equivalent, second instance is removed
a997 1
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8421> is unconnected in block <chrmemmap>.
d1000 2
a1002 1
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8441> is unconnected in block <chrmemmap>.
d1031 1
a1033 1
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8751> is unconnected in block <chrmemmap>.
a1060 1
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9051> is unconnected in block <chrmemmap>.
d1062 1
d1064 1
a1064 1
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9061> is unconnected in block <chrmemmap>.
a1091 1
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9361> is unconnected in block <chrmemmap>.
d1093 1
d1095 1
a1095 1
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9371> is unconnected in block <chrmemmap>.
d1108 1
a1110 1
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9521> is unconnected in block <chrmemmap>.
d1122 2
a1123 2
WARNING:Xst:2040 - Unit testbench: 21 multi-source signals are replaced by logic (pull-up yes): adm3a/cmattr<0>, adm3a/cmattr<1>, adm3a/cmattr<2>, adm3a/cmattr<3>, adm3a/cmattr<4>, adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N185, N187, N189, N1911, N193, N195, N197, N199.
WARNING:Xst:2042 - Unit chrmemmap: 13 internal tristates are replaced by logic (pull-up yes): attr<0>, attr<1>, attr<2>, attr<3>, attr<4>, data<0>, data<1>, data<2>, data<3>, data<4>, data<5>, data<6>, data<7>.
a1149 1
FlipFlop adm3a/vgai/sc_r_1 has been replicated 1 time(s)
a1150 4
FlipFlop adm3a/vgai/sc_r_4 has been replicated 1 time(s)
FlipFlop adm3a/vgai/sc_r_5 has been replicated 1 time(s)
FlipFlop adm3a/vgai/sc_r_6 has been replicated 1 time(s)
FlipFlop adm3a/vgai/sc_r_7 has been replicated 1 time(s)
d1152 1
a1152 1
FlipFlop cpu/addr_1 has been replicated 2 time(s)
a1154 1
FlipFlop cpu/readio has been replicated 1 time(s)
d1159 1
a1159 1
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/state_FFd7> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
d1161 1
a1161 1
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/vgai/sc_r_8> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
d1171 2
a1172 2
# Registers                                            : 668
 Flip-Flops                                            : 668
d1201 1
a1201 1
# BELS                             : 6537
d1203 11
a1213 11
#      INV                         : 104
#      LUT1                        : 233
#      LUT2                        : 416
#      LUT2_D                      : 34
#      LUT2_L                      : 11
#      LUT3                        : 1128
#      LUT3_D                      : 36
#      LUT3_L                      : 29
#      LUT4                        : 2320
#      LUT4_D                      : 88
#      LUT4_L                      : 235
d1215 4
a1218 4
#      MUXCY                       : 662
#      MUXF5                       : 609
#      MUXF6                       : 175
#      MUXF7                       : 59
d1221 2
a1222 2
#      XORCY                       : 345
# FlipFlops/Latches                : 756
d1225 2
a1226 2
#      FDCE                        : 62
#      FDE                         : 324
d1230 2
a1231 2
#      FDR                         : 75
#      FDRE                        : 39
d1233 2
a1234 2
#      FDRS                        : 47
#      FDRSE                       : 10
d1239 1
a1239 1
# RAMS                             : 844
a1241 1
#      RAMB16_S9_S9                : 1
d1248 2
a1249 2
# MULTs                            : 2
#      MULT18X18                   : 2
d1257 4
a1260 4
 Number of Slices:                    2421  out of   7680    31%  
 Number of Slice Flip Flops:           756  out of  15360     4%  
 Number of 4 input LUTs:              6314  out of  15360    41%  
    Number used as logic:             4634
d1264 2
a1265 2
 Number of BRAMs:                        4  out of     24    16%  
 Number of MULT18X18s:                   2  out of     24     8%  
d1281 1
a1281 1
clock                                                | BUFGP                          | 1509  |
d1283 4
a1286 4
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_2)| 14    |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/mask_2)| 14    |
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/comp_0)| 14    |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/comp_2)| 14    |
d1295 5
a1299 5
-----------------------------------+----------------------------------------------------+-------+
Control Signal                     | Buffer(FF name)                                    | Load  |
-----------------------------------+----------------------------------------------------+-------+
reset(reset1_INV_0:O)              | NONE(adm3a/display/vgai/gen_syncs_fit.vsync/sync_r)| 168   |
-----------------------------------+----------------------------------------------------+-------+
d1305 3
a1307 3
   Minimum period: 21.398ns (Maximum Frequency: 46.733MHz)
   Minimum input arrival time before clock: 8.800ns
   Maximum output required time after clock: 20.238ns
d1316 2
a1317 2
  Clock period: 21.398ns (frequency: 46.733MHz)
  Total number of paths / destination ports: 244771 / 9411
d1319 1
a1319 1
Delay:               10.699ns (Levels of Logic = 6)
d1329 8
a1336 8
     FDE:C->Q              6   0.720   1.071  cpu/addr_10 (cpu/addr_10)
     LUT4:I2->O            1   0.551   0.000  select1/selectc/selectout1511 (N17364)
     MUXF5:I1->O           2   0.360   1.216  select1/selectc/selectout151_f5 (select1/selectc/selectout_map6043)
     LUT4_D:I0->O          1   0.551   0.827  select1/selectc/selectout169_1 (select1/selectc/selectout169)
     LUT4_D:I3->O         14   0.551   1.255  intc/_xor00151 (intc/_xor0015)
     LUT4_D:I2->O          7   0.551   1.092  intc/_not00161 (N2811)
     LUT4:I3->O            1   0.551   0.801  intc/_not0016 (intc/_not0016)
     FDRE_1:CE                 0.602          intc/active_7
d1338 2
a1339 2
    Total                     10.699ns (4.437ns logic, 6.262ns route)
                                       (41.5% logic, 58.5% route)
d1343 1
a1343 1
  Total number of paths / destination ports: 633 / 633
d1345 1
a1345 1
Offset:              8.800ns (Levels of Logic = 2)
d1354 2
a1355 2
     BUFGP:I->O          240   0.401   3.045  reset_n_BUFGP (reset_n_BUFGP)
     INV:I->O            368   0.551   3.778  reset1_INV_0 (reset)
d1358 2
a1359 2
    Total                      8.800ns (1.978ns logic, 6.822ns route)
                                       (22.5% logic, 77.5% route)
d1374 1
a1374 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15524)
d1393 1
a1393 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15524)
d1412 1
a1412 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15524)
d1431 1
a1431 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15524)
d1441 2
a1442 2
Offset:              20.238ns (Levels of Logic = 10)
  Source:            cpu/addr_2 (FF)
d1446 1
a1446 1
  Data Path: cpu/addr_2 to data<7>
d1450 9
a1458 10
     FDE:C->Q             29   0.720   2.031  cpu/addr_2 (cpu/addr_2)
     LUT4:I1->O            1   0.551   0.000  _and0000_inv168_SW01 (N17393)
     MUXF5:I1->O           2   0.360   0.903  _and0000_inv168_SW0_f5 (N16510)
     LUT4:I3->O            1   0.551   0.000  _and0000_inv1682 (N17396)
     MUXF5:I0->O           1   0.360   0.827  _and0000_inv168_f5 (_and0000_inv_map5607)
     LUT4:I3->O            9   0.551   1.192  _and0000_inv211 (_and0000_inv)
     LUT4:I2->O            1   0.551   1.140  N185LogicTrst120 (N185LogicTrst1_map5693)
     LUT4:I0->O            1   0.551   0.827  N185LogicTrst142_SW0 (N17018)
     LUT4:I3->O           16   0.551   1.576  N185LogicTrst142 (N256)
     LUT3:I0->O            1   0.551   0.801  N197LogicTrst115 (data_1_IOBUF)
d1461 2
a1462 2
    Total                     20.238ns (10.941ns logic, 9.297ns route)
                                       (54.1% logic, 45.9% route)
d1466 1
a1466 1
  Total number of paths / destination ports: 552 / 8
d1468 1
a1468 1
Offset:              16.200ns (Levels of Logic = 7)
d1477 9
a1485 7
     LDCE:G->Q             7   0.633   1.405  select1/selectc/mask_1 (select1/selectc/mask_1)
     LUT4:I0->O            1   0.551   0.000  select1/selectc/selectout1511 (N17364)
     MUXF5:I1->O           2   0.360   1.216  select1/selectc/selectout151_f5 (select1/selectc/selectout_map6043)
     LUT4_D:I0->LO         1   0.551   0.126  select1/selectc/selectout169_1 (N17618)
     LUT4:I3->O           17   0.551   1.684  intc/_not0027_SW0 (intc/_and0009)
     LUT4:I0->O           16   0.551   1.576  N185LogicTrst142 (N256)
     LUT3:I0->O            1   0.551   0.801  N197LogicTrst115 (data_1_IOBUF)
d1488 2
a1489 2
    Total                     16.200ns (9.392ns logic, 6.808ns route)
                                       (58.0% logic, 42.0% route)
d1495 1
a1495 1
Offset:              17.126ns (Levels of Logic = 8)
d1505 4
a1508 4
     LUT4:I0->O            1   0.551   0.000  select1/select248_SW02 (N17390)
     MUXF5:I0->O           2   0.360   1.216  select1/select248_SW0_f5 (N16508)
     LUT4:I0->O            1   0.551   0.000  select1/select2482 (N17392)
     MUXF5:I0->O           2   0.360   1.216  select1/select248_f5 (select1/select2_map5499)
d1510 4
a1513 2
     LUT4:I1->O           16   0.551   1.576  N185LogicTrst142 (N256)
     LUT3:I0->O            1   0.551   0.801  N197LogicTrst115 (data_1_IOBUF)
d1516 2
a1517 2
    Total                     17.126ns (9.752ns logic, 7.374ns route)
                                       (56.9% logic, 43.1% route)
d1523 1
a1523 1
Offset:              19.715ns (Levels of Logic = 9)
d1533 7
a1539 8
     LUT4:I0->O            1   0.551   0.000  _and0000_inv181 (N17350)
     MUXF5:I1->O           1   0.360   1.140  _and0000_inv18_f5 (_and0000_inv_map5561)
     LUT4:I0->O            1   0.551   1.140  _and0000_inv108 (_and0000_inv_map5588)
     LUT4:I0->O            9   0.551   1.192  _and0000_inv211 (_and0000_inv)
     LUT4:I2->O            1   0.551   1.140  N185LogicTrst120 (N185LogicTrst1_map5693)
     LUT4:I0->O            1   0.551   0.827  N185LogicTrst142_SW0 (N17018)
     LUT4:I3->O           16   0.551   1.576  N185LogicTrst142 (N256)
     LUT3:I0->O            1   0.551   0.801  N197LogicTrst115 (data_1_IOBUF)
d1542 2
a1543 2
    Total                     19.715ns (10.494ns logic, 9.221ns route)
                                       (53.2% logic, 46.8% route)
d1549 1
a1549 1
Offset:              17.403ns (Levels of Logic = 8)
d1558 9
a1566 9
     LDCE:G->Q             7   0.633   1.405  select1/selectd/mask_1 (select1/selectd/mask_1)
     LUT4:I0->O            1   0.551   0.000  select1/selectd/selectout791 (N17330)
     MUXF5:I1->O           1   0.360   1.140  select1/selectd/selectout79_f5 (select1/selectd/selectout_map5389)
     LUT4_D:I0->O          8   0.551   1.278  select1/selectd/selectout169 (select1/selectd/selectout_map5416)
     LUT4:I1->O            1   0.551   0.827  N187LogicTrst127_SW0_SW0 (N17028)
     LUT4:I3->O            1   0.551   1.140  N187LogicTrst127_SW0 (N16922)
     LUT4:I0->O            1   0.551   0.869  N187LogicTrst127 (N187LogicTrst_map5838)
     LUT3:I2->O            1   0.551   0.801  N187LogicTrst134 (data_6_IOBUF)
     IOBUF:I->IO               5.644          data_6_IOBUF (data<6>)
d1568 2
a1569 2
    Total                     17.403ns (9.943ns logic, 7.460ns route)
                                       (57.1% logic, 42.9% route)
d1575 1
a1575 1
Offset:              15.912ns (Levels of Logic = 7)
d1585 5
a1589 5
     LUT4:I2->O            1   0.551   0.996  N193LogicTrst26 (N193LogicTrst_map5708)
     LUT4:I1->O            1   0.551   0.827  N193LogicTrst34 (N193LogicTrst_map5710)
     LUT4:I3->O            1   0.551   0.827  N193LogicTrst61 (N193LogicTrst_map5716)
     LUT4:I3->O            1   0.551   1.140  N193LogicTrst97_SW0 (N16914)
     LUT4:I0->O            1   0.551   0.869  N193LogicTrst97 (N193LogicTrst_map5723)
d1593 2
a1594 2
    Total                     15.912ns (9.583ns logic, 6.329ns route)
                                       (60.2% logic, 39.8% route)
d1615 1
a1615 1
CPU : 204.47 / 204.97 s | Elapsed : 205.00 / 205.00 s
d1619 1
a1619 1
Total memory usage is 239120 kilobytes
d1622 2
a1623 2
Number of warnings :  162 (   0 filtered)
Number of infos    :   14 (   0 filtered)
@


1.1.1.6
log
@8080 CPU project
@
text
@d4 1
a4 1
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 1.00 s
d7 1
a7 1
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 1.00 s
d104 5
a108 2
Architecture vga_arch of Entity vga is up to date.
Architecture sync_arch of Entity sync is up to date.
d268 1
a268 1
    Found 2048x8-bit ROM for signal <datao>.
d358 7
a364 7
    Found 5-bit adder for signal <$add0001> created at line 1534.
    Found 8-bit adder carry out for signal <$addsub0000> created at line 1527.
    Found 4-bit adder carry out for signal <$addsub0001> created at line 1528.
    Found 6-bit subtractor for signal <$sub0000> created at line 1540.
    Found 6-bit subtractor for signal <$sub0001> created at line 1546.
    Found 9-bit subtractor for signal <$sub0002> created at line 1539.
    Found 8-bit xor2 for signal <$xor0000> created at line 1557.
d453 4
a456 4
    | States             | 36                                             |
    | Transitions        | 917                                            |
    | Inputs             | 141                                            |
    | Outputs            | 35                                             |
d464 1
a464 1
    Found 4x16-bit ROM for signal <$mux0042> created at line 263.
d472 9
a480 9
    Found 32-bit adder for signal <$add0001> created at line 494.
    Found 32-bit adder for signal <$add0002> created at line 506.
    Found 32-bit adder for signal <$add0003> created at line 518.
    Found 16-bit adder for signal <$add0004> created at line 974.
    Found 16-bit adder for signal <$add0005> created at line 889.
    Found 32-bit adder for signal <$add0006> created at line 563.
    Found 32-bit adder for signal <$add0007> created at line 551.
    Found 32-bit adder for signal <$add0008> created at line 539.
    Found 17-bit adder for signal <$add0009> created at line 484.
d488 1
a488 1
    Found 16-bit adder for signal <$addsub0007> created at line 1045.
d490 1
a490 1
    Found 16-bit adder for signal <$addsub0009> created at line 1086.
d492 1
a492 1
    Found 4-bit adder carry out for signal <$addsub0011> created at line 359.
d494 6
a499 6
    Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 356.
    Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1339.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0022> created at line 312.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0023> created at line 312.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 312.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 312.
d501 1
a501 1
    Found 3-bit 4-to-1 multiplexer for signal <$mux0050> created at line 316.
d503 6
a508 6
    Found 16-bit adder for signal <$share0000> created at line 312.
    Found 16-bit addsub for signal <$share0006> created at line 263.
    Found 32-bit subtractor for signal <$sub0000> created at line 539.
    Found 32-bit subtractor for signal <$sub0001> created at line 551.
    Found 32-bit subtractor for signal <$sub0002> created at line 563.
    Found 16-bit subtractor for signal <$sub0003> created at line 760.
d619 1
a619 1
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <fchsta> of Case statement line 873 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
d637 1
a637 1
WARNING:Xst:643 - "vgachr.v" line 945: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
d640 22
a661 22
    Found 11-bit adder for signal <$add0000> created at line 928.
    Found 9-bit subtractor for signal <$addsub0000> created at line 945.
    Found 11-bit adder for signal <$addsub0001> created at line 945.
    Found 11-bit comparator equal for signal <$cmp_eq0003> created at line 882.
    Found 32-bit comparator greatequal for signal <$cmp_ge0000> created at line 814.
    Found 7-bit comparator greatequal for signal <$cmp_ge0001> created at line 854.
    Found 5-bit comparator greatequal for signal <$cmp_ge0002> created at line 858.
    Found 7-bit comparator less for signal <$cmp_lt0000> created at line 854.
    Found 5-bit comparator less for signal <$cmp_lt0001> created at line 858.
    Found 8-bit comparator less for signal <$cmp_lt0002> created at line 945.
    Found 9x6-bit multiplier for signal <$mult0002> created at line 945.
    Found 16-bit 4-to-1 multiplexer for signal <$mux0000> created at line 911.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0001> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0002> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0003> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0004> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0006> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0007> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0008> created at line 904.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0009> created at line 883.
    Found 1-bit xor2 for signal <$xor0000> created at line 903.
d704 2
a705 2
WARNING:Xst:643 - "vgachr.v" line 688: The result of a 9x8-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 4x1-bit ROM for signal <$mux0023> created at line 372.
d707 3
a709 3
    Found 11-bit adder for signal <$add0002> created at line 558.
    Found 9-bit subtractor for signal <$addsub0000> created at line 688.
    Found 11-bit adder for signal <$addsub0001> created at line 521.
d711 21
a731 21
    Found 11-bit adder carry out for signal <$addsub0003> created at line 541.
    Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 384.
    Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 413.
    Found 8-bit comparator greatequal for signal <$cmp_ge0002> created at line 685.
    Found 8-bit comparator greatequal for signal <$cmp_ge0003> created at line 358.
    Found 8-bit comparator greatequal for signal <$cmp_ge0004> created at line 361.
    Found 12-bit comparator greater for signal <$cmp_gt0000> created at line 541.
    Found 8-bit comparator greater for signal <$cmp_gt0001> created at line 707.
    Found 11-bit comparator greater for signal <$cmp_gt0002> created at line 425.
    Found 12-bit comparator greater for signal <$cmp_gt0003> created at line 541.
    Found 8-bit comparator lessequal for signal <$cmp_le0000> created at line 685.
    Found 8-bit comparator lessequal for signal <$cmp_le0001> created at line 685.
    Found 8-bit comparator lessequal for signal <$cmp_le0002> created at line 358.
    Found 8-bit comparator lessequal for signal <$cmp_le0003> created at line 361.
    Found 11-bit comparator less for signal <$cmp_lt0000> created at line 398.
    Found 11-bit comparator less for signal <$cmp_lt0001> created at line 519.
    Found 11-bit comparator less for signal <$cmp_lt0002> created at line 555.
    Found 11-bit comparator less for signal <$cmp_lt0003> created at line 603.
    Found 8-bit comparator less for signal <$cmp_lt0004> created at line 707.
    Found 11-bit comparator less for signal <$cmp_lt0005> created at line 432.
    Found 9x8-bit multiplier for signal <$mult0002> created at line 688.
d734 3
a736 3
    Found 11-bit addsub for signal <$share0000> created at line 372.
    Found 10-bit subtractor for signal <$sub0000> created at line 688.
    Found 5-bit subtractor for signal <$sub0001> created at line 708.
d791 3
a793 3
 2048x8-bit ROM                                        : 2
 4x1-bit ROM                                           : 1
 4x16-bit ROM                                          : 1
d919 2
a920 2
Optimizing FSM <cpu/state> on signal <state[1:38]> with speed1 encoding.
--------------------------------------------------
d922 32
a953 32
--------------------------------------------------
 000001 | 10000000000000000000000000000000000000
 000010 | 01000000000000000000000000000000000000
 000011 | 00100000000000000000000000000000000000
 000100 | 00010000000000000000000000000000000000
 000101 | 00000000100000000000000000000000000000
 000110 | 00000000010010000000000000000000000000
 000111 | 00000100000010000000000000000000000000
 001000 | 00000000000010000100000000000000000000
 001001 | 00000000000010000001000000000000000000
 001010 | 00000000000010000000010000000000000000
 001011 | 00000000000010000000001000000000000000
 001100 | 00000000001000000000100000000000000000
 001101 | 00000000000010000000000000010000000000
 001110 | 00000010000000000000000000000000000000
 001111 | 00000000000001000000000000000000000000
 010000 | 00000000000000100000000000000000000000
 010001 | 00000000001000010000000000000000000000
 010010 | 00000001000000000000000000000000000000
 010011 | 00000000000000000000000000000000000010
 010100 | 00000000001100000000000000000000000000
 010101 | 00000000000010000000000100000000000000
 010110 | 00000000000000000000000000000010000000
 010111 | 00000000000000000000000000000100000000
 011000 | 00000000000010000000000000000001000000
 011001 | 00000000000000000000000000000000100000
 011010 | 00000000000000000000000000000000001000
 011011 | 00000000000000000000000000000000000100
 011100 | 00000000000010000000000000000000000001
 011101 | 00000000001000001000000000000000000000
 011110 | 00000000001000000000000010000000000000
 011111 | 00000000001000000000000000100000000000
d955 4
a958 6
 100000 | 00000000001000000010000000000000000000
 100001 | 00000000000000000000000001000000000000
 100010 | 00001000000010000000000000000000000000
 100011 | 00000000000010000000000000001000000000
 100100 | 00000000000010000000000000000000010000
--------------------------------------------------
d972 1
a972 1
INFO:Xst:1651 - Address input of ROM <rom/Mrom_datao> is tied to register <cpu/addr>.
d991 1
a994 1
 2048x8-bit single-port block RAM                      : 1
d997 1
a997 2
 4x1-bit ROM                                           : 1
 4x16-bit ROM                                          : 1
d1031 2
a1032 2
# Registers                                            : 577
 Flip-Flops                                            : 577
d1203 1
a1203 1
WARNING:Xst:2040 - Unit testbench: 21 multi-source signals are replaced by logic (pull-up yes): adm3a/cmattr<0>, adm3a/cmattr<1>, adm3a/cmattr<2>, adm3a/cmattr<3>, adm3a/cmattr<4>, adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N186, N188, N190, N192, N194, N196, N198, N200.
d1221 1
a1221 1
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 33.
a1229 1
FlipFlop adm3a/display/rowcnt_0 has been replicated 1 time(s)
d1231 2
d1234 1
d1236 1
d1247 2
a1248 2
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <cpu/state_FFd3> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <adm3a/vgai/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
d1258 2
a1259 2
# Registers                                            : 667
 Flip-Flops                                            : 667
d1288 1
a1288 1
# BELS                             : 6524
d1290 1
a1290 1
#      INV                         : 101
d1292 9
a1300 9
#      LUT2                        : 429
#      LUT2_D                      : 37
#      LUT2_L                      : 10
#      LUT3                        : 1123
#      LUT3_D                      : 44
#      LUT3_L                      : 35
#      LUT4                        : 2288
#      LUT4_D                      : 85
#      LUT4_L                      : 255
d1303 2
a1304 2
#      MUXF5                       : 588
#      MUXF6                       : 177
d1309 1
a1309 1
# FlipFlops/Latches                : 755
d1312 1
a1312 1
#      FDCE                        : 58
d1317 2
a1318 2
#      FDR                         : 77
#      FDRE                        : 40
d1345 4
a1348 4
 Number of Slices:                    2422  out of   7680    31%  
 Number of Slice Flip Flops:           755  out of  15360     4%  
 Number of 4 input LUTs:              6320  out of  15360    41%  
    Number used as logic:             4640
d1369 1
a1369 1
clock                                                | BUFGP                          | 1508  |
d1371 4
a1374 4
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/comp_2)| 14    |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_0)| 14    |
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/comp_2)| 14    |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/mask_1)| 14    |
d1383 5
a1387 5
-----------------------------------+----------------------------+-------+
Control Signal                     | Buffer(FF name)            | Load  |
-----------------------------------+----------------------------+-------+
reset(reset1_INV_0:O)              | NONE(adm3a/vgai/timer_r_11)| 164   |
-----------------------------------+----------------------------+-------+
d1393 3
a1395 3
   Minimum period: 21.176ns (Maximum Frequency: 47.223MHz)
   Minimum input arrival time before clock: 8.789ns
   Maximum output required time after clock: 18.905ns
d1404 2
a1405 2
  Clock period: 21.176ns (frequency: 47.223MHz)
  Total number of paths / destination ports: 239144 / 9408
d1407 1
a1407 1
Delay:               10.588ns (Levels of Logic = 6)
d1418 2
a1419 2
     LUT4:I2->O            1   0.551   0.000  select1/selectc/selectout1511 (N17408)
     MUXF5:I1->O           2   0.360   1.216  select1/selectc/selectout151_f5 (select1/selectc/selectout_map6135)
d1421 2
a1422 2
     LUT4_D:I3->O         12   0.551   1.144  intc/_not0027_SW0 (intc/_and0009)
     LUT4_D:I3->O          7   0.551   1.092  intc/_not00161 (N288)
d1426 2
a1427 2
    Total                     10.588ns (4.437ns logic, 6.151ns route)
                                       (41.9% logic, 58.1% route)
d1431 1
a1431 1
  Total number of paths / destination ports: 636 / 636
d1433 1
a1433 1
Offset:              8.789ns (Levels of Logic = 2)
d1443 1
a1443 1
     INV:I->O            366   0.551   3.766  reset1_INV_0 (reset)
d1446 1
a1446 1
    Total                      8.789ns (1.978ns logic, 6.811ns route)
d1462 1
a1462 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15734)
d1481 1
a1481 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15734)
d1500 1
a1500 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15734)
d1519 1
a1519 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N15734)
d1527 1
a1527 1
  Total number of paths / destination ports: 2377 / 47
d1529 2
a1530 2
Offset:              18.905ns (Levels of Logic = 8)
  Source:            cpu/addr_4 (FF)
d1534 1
a1534 1
  Data Path: cpu/addr_4 to data<7>
d1538 11
a1548 9
     FDE:C->Q              8   0.720   1.278  cpu/addr_4 (cpu/addr_4)
     LUT4:I1->O            3   0.551   1.246  select1/selacc426 (select1/selacc4_map5456)
     LUT2:I0->O            3   0.551   1.246  select1/selacc454 (select1/selacc)
     LUT4:I0->O            9   0.551   1.150  select1/selecta/_and0001_inv1 (select1/selecta/_and0001_inv)
     LUT4:I3->O            1   0.551   0.996  N192LogicTrst63_SW0 (N16695)
     LUT4:I1->O            1   0.551   1.140  N192LogicTrst63 (N192LogicTrst_map6014)
     LUT4:I0->O            1   0.551   0.827  N192LogicTrst126_SW0 (N16697)
     LUT4:I3->O            1   0.551   0.801  N192LogicTrst126 (data_4_IOBUF)
     IOBUF:I->IO               5.644          data_4_IOBUF (data<4>)
d1550 1
a1550 1
    Total                     18.905ns (10.221ns logic, 8.684ns route)
d1554 2
a1555 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
  Total number of paths / destination ports: 840 / 8
d1557 2
a1558 2
Offset:              18.295ns (Levels of Logic = 8)
  Source:            select1/selecta/mask_1 (LATCH)
d1560 1
a1560 1
  Source Clock:      select1/selecta/_and0000 falling
d1562 1
a1562 1
  Data Path: select1/selecta/mask_1 to data<7>
d1566 8
a1573 9
     LDCE:G->Q             7   0.633   1.405  select1/selecta/mask_1 (select1/selecta/mask_1)
     LUT4:I0->O            1   0.551   0.000  _and0000_inv181 (N17398)
     MUXF5:I1->O           1   0.360   1.140  _and0000_inv18_f5 (_and0000_inv_map5666)
     LUT4:I0->O            1   0.551   1.140  _and0000_inv108 (_and0000_inv_map5693)
     LUT4:I0->O            9   0.551   1.150  _and0000_inv211 (_and0000_inv)
     LUT4:I3->O            1   0.551   1.140  N186LogicTrst120 (N186LogicTrst1_map5798)
     LUT4:I0->O           16   0.551   1.576  N186LogicTrst142 (N260)
     LUT3:I0->O            1   0.551   0.801  N200LogicTrst108 (data_0_IOBUF)
     IOBUF:I->IO               5.644          data_0_IOBUF (data<0>)
d1575 2
a1576 2
    Total                     18.295ns (9.943ns logic, 8.352ns route)
                                       (54.3% logic, 45.7% route)
d1579 2
a1580 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectd/_and0000'
  Total number of paths / destination ports: 624 / 8
d1582 2
a1583 2
Offset:              17.494ns (Levels of Logic = 8)
  Source:            select1/selectd/mask_1 (LATCH)
d1585 1
a1585 1
  Source Clock:      select1/selectd/_and0000 falling
d1587 1
a1587 1
  Data Path: select1/selectd/mask_1 to data<7>
d1591 9
a1599 9
     LDCE:G->Q             7   0.633   1.405  select1/selectd/mask_1 (select1/selectd/mask_1)
     LUT4:I0->O            1   0.551   0.000  select1/selectd/selectout791 (N17378)
     MUXF5:I1->O           1   0.360   1.140  select1/selectd/selectout79_f5 (select1/selectd/selectout_map5494)
     LUT4_D:I0->O          3   0.551   0.975  select1/selectd/selectout169 (select1/selectd/selectout_map5521)
     LUT3:I2->O           16   0.551   1.576  adm3a/_and00001 (adm3a/_and0000)
     LUT4:I0->O            1   0.551   0.827  N188LogicTrst113 (N188LogicTrst_map5932)
     LUT4:I3->O            1   0.551   0.827  N188LogicTrst126_SW0 (N16685)
     LUT4:I3->O            1   0.551   0.801  N188LogicTrst126 (data_6_IOBUF)
     IOBUF:I->IO               5.644          data_6_IOBUF (data<6>)
d1601 2
a1602 2
    Total                     17.494ns (9.943ns logic, 7.551ns route)
                                       (56.8% logic, 43.2% route)
d1605 1
a1605 1
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'
d1608 2
a1609 2
Offset:              16.855ns (Levels of Logic = 8)
  Source:            select1/selectb/comp_1 (LATCH)
d1611 1
a1611 1
  Source Clock:      select1/selectb/_and0000 falling
d1613 1
a1613 1
  Data Path: select1/selectb/comp_1 to data<7>
d1617 10
a1626 9
     LDCE:G->Q             3   0.633   1.246  select1/selectb/comp_1 (select1/selectb/comp_1)
     LUT4:I0->O            1   0.551   0.000  select1/select248_SW02 (N17432)
     MUXF5:I0->O           2   0.360   1.072  select1/select248_SW0_f5 (N16565)
     LUT4:I1->O            1   0.551   0.000  select1/select2482 (N17434)
     MUXF5:I0->O           2   0.360   1.216  select1/select248_f5 (select1/select2_map5604)
     LUT4:I0->O            9   0.551   1.192  ram/_and0000_inv1 (ram/_and0000_inv)
     LUT4:I2->O           16   0.551   1.576  N186LogicTrst142 (N260)
     LUT3:I0->O            1   0.551   0.801  N200LogicTrst108 (data_0_IOBUF)
     IOBUF:I->IO               5.644          data_0_IOBUF (data<0>)
d1628 2
a1629 2
    Total                     16.855ns (9.752ns logic, 7.103ns route)
                                       (57.9% logic, 42.1% route)
d1632 2
a1633 2
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
  Total number of paths / destination ports: 552 / 8
d1635 2
a1636 2
Offset:              18.172ns (Levels of Logic = 8)
  Source:            select1/selectc/mask_1 (LATCH)
d1638 1
a1638 1
  Source Clock:      select1/selectc/_and0000 falling
d1640 1
a1640 1
  Data Path: select1/selectc/mask_1 to data<7>
d1644 9
a1652 9
     LDCE:G->Q             7   0.633   1.405  select1/selectc/mask_1 (select1/selectc/mask_1)
     LUT4:I0->O            1   0.551   0.000  select1/selectc/selectout1511 (N17408)
     MUXF5:I1->O           2   0.360   1.216  select1/selectc/selectout151_f5 (select1/selectc/selectout_map6135)
     LUT4_D:I0->O          1   0.551   0.827  select1/selectc/selectout169_1 (select1/selectc/selectout169)
     LUT4_D:I3->O         12   0.551   1.457  intc/_not0027_SW0 (intc/_and0009)
     LUT2:I0->O            5   0.551   0.947  intc/_or0000_inv1 (intc/_or0000_inv)
     LUT4:I3->O           16   0.551   1.576  N186LogicTrst142 (N260)
     LUT3:I0->O            1   0.551   0.801  N200LogicTrst108 (data_0_IOBUF)
     IOBUF:I->IO               5.644          data_0_IOBUF (data<0>)
d1654 2
a1655 2
    Total                     18.172ns (9.943ns logic, 8.229ns route)
                                       (54.7% logic, 45.3% route)
d1661 1
a1661 1
Offset:              15.954ns (Levels of Logic = 7)
d1671 6
a1676 6
     LUT4:I2->O            1   0.551   0.996  N194LogicTrst26 (N194LogicTrst_map5813)
     LUT4:I1->O            1   0.551   0.827  N194LogicTrst34 (N194LogicTrst_map5815)
     LUT4:I3->O            1   0.551   0.869  N194LogicTrst61 (N194LogicTrst_map5821)
     LUT3:I2->O            1   0.551   1.140  N194LogicTrst95_SW0 (N16958)
     LUT4:I0->O            1   0.551   0.869  N194LogicTrst95 (N194LogicTrst_map5827)
     LUT3:I2->O            1   0.551   0.801  N194LogicTrst108 (data_3_IOBUF)
d1679 2
a1680 2
    Total                     15.954ns (9.583ns logic, 6.371ns route)
                                       (60.1% logic, 39.9% route)
d1701 1
a1701 1
CPU : 214.69 / 214.91 s | Elapsed : 214.00 / 215.00 s
d1705 1
a1705 1
Total memory usage is 240144 kilobytes
@


1.1.1.7
log
@8080 CPU project
@
text
@d4 1
a4 1
CPU : 0.00 / 0.50 s | Elapsed : 0.00 / 0.00 s
d7 1
a7 1
CPU : 0.00 / 0.50 s | Elapsed : 0.00 / 0.00 s
d355 7
a361 7
    Found 5-bit adder for signal <$add0001> created at line 1578.
    Found 8-bit adder carry out for signal <$addsub0000> created at line 1571.
    Found 4-bit adder carry out for signal <$addsub0001> created at line 1572.
    Found 6-bit subtractor for signal <$sub0000> created at line 1584.
    Found 6-bit subtractor for signal <$sub0001> created at line 1590.
    Found 9-bit subtractor for signal <$sub0002> created at line 1583.
    Found 8-bit xor2 for signal <$xor0000> created at line 1601.
d450 4
a453 4
    | States             | 39                                             |
    | Transitions        | 1171                                           |
    | Inputs             | 148                                            |
    | Outputs            | 38                                             |
d461 1
a461 1
    Found 4x16-bit ROM for signal <$mux0041> created at line 268.
d469 9
a477 9
    Found 32-bit adder for signal <$add0000> created at line 501.
    Found 32-bit adder for signal <$add0001> created at line 513.
    Found 32-bit adder for signal <$add0002> created at line 525.
    Found 16-bit adder for signal <$add0003> created at line 980.
    Found 16-bit adder for signal <$add0004> created at line 895.
    Found 32-bit adder for signal <$add0005> created at line 570.
    Found 32-bit adder for signal <$add0006> created at line 558.
    Found 32-bit adder for signal <$add0007> created at line 546.
    Found 17-bit adder for signal <$add0008> created at line 491.
d485 1
a485 1
    Found 16-bit adder for signal <$addsub0007> created at line 1092.
d487 1
a487 1
    Found 16-bit adder for signal <$addsub0009> created at line 1051.
d489 17
a505 13
    Found 8-bit adder carry out for signal <$addsub0011>.
    Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 1373.
    Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 361.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 317.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 317.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0044> created at line 321.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0045>.
    Found 16-bit adder for signal <$share0000> created at line 317.
    Found 16-bit addsub for signal <$share0006> created at line 268.
    Found 32-bit subtractor for signal <$sub0000> created at line 546.
    Found 32-bit subtractor for signal <$sub0001> created at line 558.
    Found 32-bit subtractor for signal <$sub0002> created at line 570.
    Found 16-bit subtractor for signal <$sub0003> created at line 766.
d537 1
a537 1
	inferred  33 Adder/Subtractor(s).
d539 1
a539 1
	inferred  38 Multiplexer(s).
d794 1
a794 1
# Adders/Subtractors                                   : 55
d806 1
a806 1
 4-bit adder carry out                                 : 1
d858 1
a858 1
# Multiplexers                                         : 29
d862 2
a863 2
 3-bit 4-to-1 multiplexer                              : 2
 8-bit 4-to-1 multiplexer                              : 3
d916 2
a917 2
Optimizing FSM <cpu/state> on signal <state[1:41]> with speed1 encoding.
-----------------------------------------------------
d919 32
a950 32
-----------------------------------------------------
 000001 | 10000000000000000000000000000000000000000
 000010 | 01000000000000000000000000000000000000000
 000011 | 00100000000000000000000000000000000000000
 000100 | 00010000000000000000000000000000000000000
 000101 | 00000000100000000000000000000000000000000
 000110 | 00000000010000000000000000000000000000001
 000111 | 00000010000000000000000000000000000000001
 001000 | 00000000000000001000000000000000000000001
 001001 | 00000000000000000010000000000000000000001
 001010 | 00000000000000000000100000000000000000001
 001011 | 00000000000000000000010000000000000000001
 001100 | 00000000001000000001000000000000000000000
 001101 | 00000000000000000000000000100000000000001
 001110 | 00000001000000000000000000000000000000000
 001111 | 00000000000010000000000000000000000000000
 010000 | 00000000000001000000000000000000000000000
 010001 | 00000000001000100000000000000000000000000
 010010 | 00000100000000000000000000000000000000000
 010011 | 00000000000000000000000000000000100000000
 010100 | 00000000001100000000000000000000000000000
 010101 | 00000000000000000000001000000000000000001
 010110 | 00000000000000000000000000000010000000000
 010111 | 00000000000000000000000000000000000100000
 011000 | 00000000000000000000000000000000000010001
 011001 | 00000000000000000000000000000001000000000
 011010 | 00000000000000000000000000000000000001000
 011011 | 00000000000000000000000000000000000000100
 011100 | 00000000000000000000000000000000000000011
 011101 | 00000000001000010000000000000000000000000
 011110 | 00000000001000000000000100000000000000000
 011111 | 00000000001000000000000001000000000000000
d952 6
a957 9
 100000 | 00000000001000000100000000000000000000000
 100001 | 00000000000000000000000010000000000000000
 100010 | 00001000000000000000000000000000000000001
 100011 | 00000000000000000000000000001000000000001
 100100 | 00000000000000000000000000000000010000001
 100101 | 00000000001000000000000000010000000000000
 100110 | 00000000001000000000000000000000001000000
 100111 | 00000000001000000000000000000100000000000
-----------------------------------------------------
d1001 1
a1001 1
# Adders/Subtractors                                   : 55
d1013 1
a1013 1
 4-bit adder carry out                                 : 1
d1031 2
a1032 2
# Registers                                            : 580
 Flip-Flops                                            : 580
d1054 1
a1054 1
# Multiplexers                                         : 29
d1058 2
a1059 2
 3-bit 4-to-1 multiplexer                              : 2
 8-bit 4-to-1 multiplexer                              : 3
d1203 1
a1203 1
WARNING:Xst:2040 - Unit testbench: 21 multi-source signals are replaced by logic (pull-up yes): adm3a/cmattr<0>, adm3a/cmattr<1>, adm3a/cmattr<2>, adm3a/cmattr<3>, adm3a/cmattr<4>, adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N180, N182, N184, N186, N188, N190, N192, N194.
d1231 3
a1233 1
FlipFlop adm3a/vgai/sc_r_5 has been replicated 1 time(s)
d1255 2
a1256 2
# Registers                                            : 668
 Flip-Flops                                            : 668
d1285 1
a1285 1
# BELS                             : 6513
d1288 10
a1297 10
#      LUT1                        : 231
#      LUT2                        : 439
#      LUT2_D                      : 36
#      LUT2_L                      : 5
#      LUT3                        : 1122
#      LUT3_D                      : 37
#      LUT3_L                      : 25
#      LUT4                        : 2308
#      LUT4_D                      : 82
#      LUT4_L                      : 236
d1299 3
a1301 3
#      MUXCY                       : 655
#      MUXF5                       : 612
#      MUXF6                       : 175
d1305 2
a1306 2
#      XORCY                       : 337
# FlipFlops/Latches                : 756
d1309 1
a1309 1
#      FDCE                        : 56
d1314 1
a1314 1
#      FDR                         : 81
d1317 1
a1317 1
#      FDRS                        : 46
d1342 4
a1345 4
 Number of Slices:                    2416  out of   7680    31%  
 Number of Slice Flip Flops:           756  out of  15360     4%  
 Number of 4 input LUTs:              6302  out of  15360    41%  
    Number used as logic:             4622
d1366 1
a1366 1
clock                                                | BUFGP                          | 1509  |
d1368 4
a1371 4
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_5)| 14    |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_2)| 14    |
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/mask_7)| 14    |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/mask_7)| 14    |
d1380 5
a1384 5
-----------------------------------+------------------------------------------------------+-------+
Control Signal                     | Buffer(FF name)                                      | Load  |
-----------------------------------+------------------------------------------------------+-------+
reset(reset1_INV_0:O)              | NONE(adm3a/display/vgai/gen_syncs_fit.vsync/cnt_r_10)| 162   |
-----------------------------------+------------------------------------------------------+-------+
d1390 2
a1391 2
   Minimum period: 21.437ns (Maximum Frequency: 46.649MHz)
   Minimum input arrival time before clock: 8.841ns
d1401 2
a1402 2
  Clock period: 21.437ns (frequency: 46.649MHz)
  Total number of paths / destination ports: 238171 / 9398
d1404 3
a1406 3
Delay:               21.437ns (Levels of Logic = 15)
  Source:            adm3a/display/curchr_6 (FF)
  Destination:       adm3a/display/pixeldata_10 (FF)
d1408 1
a1408 1
  Destination Clock: clock rising
d1410 1
a1410 1
  Data Path: adm3a/display/curchr_6 to adm3a/display/pixeldata_10
d1414 8
a1421 17
     FD:C->Q               2   0.720   0.877  adm3a/display/curchr_6 (adm3a/display/curchr_6)
     MULT18X18:A0->P0     39   1.779   2.088  adm3a/display/Mmult__mult0002 (adm3a/display/_mult0002<0>)
     LUT2:I1->O            1   0.551   0.000  adm3a/display/Madd__addsub0001_lut<0>_1 (adm3a/display/Madd__addsub0001_lut<0>)
     MUXCY:S->O            1   0.500   0.000  adm3a/display/Madd__addsub0001_cy<0> (adm3a/display/Madd__addsub0001_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  adm3a/display/Madd__addsub0001_cy<1> (adm3a/display/Madd__addsub0001_cy<1>)
     XORCY:CI->O         145   0.904   2.526  adm3a/display/Madd__addsub0001_xor<2> (adm3a/display/_addsub0001<2>)
     LUT4_D:I3->O          1   0.551   0.869  adm3a/display/crom/Mrom_data145_SW3 (N16984)
     LUT4:I2->O            7   0.551   1.092  adm3a/display/crom/Mrom_data145 (adm3a/display/N149)
     LUT4:I3->O            1   0.551   0.827  adm3a/display/chradr<4>173 (adm3a/display/N19411)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/chradr<7>1555_G (N17173)
     MUXF5:I1->O           1   0.360   0.827  adm3a/display/chradr<7>1555 (adm3a/display/chradr<7>15_map5531)
     LUT4:I3->O            1   0.551   0.827  adm3a/display/chradr<7>1557 (adm3a/display/chradr<7>12)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/chradr<9>_f5_2_F (N17190)
     MUXF5:I0->O           1   0.360   0.827  adm3a/display/chradr<9>_f5_2 (adm3a/display/chradr<9>_f53)
     LUT4_D:I3->O          1   0.551   0.827  adm3a/display/chradr<10>111411 (adm3a/display/N2731)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/_mux0011<10>1 (adm3a/display/_mux0011<10>)
     FDE:D                     0.203          adm3a/display/pixeldata_10
d1423 2
a1424 2
    Total                     21.437ns (9.849ns logic, 11.588ns route)
                                       (45.9% logic, 54.1% route)
d1428 1
a1428 1
  Total number of paths / destination ports: 639 / 639
d1430 1
a1430 1
Offset:              8.841ns (Levels of Logic = 2)
d1439 3
a1441 3
     BUFGP:I->O          248   0.401   3.090  reset_n_BUFGP (reset_n_BUFGP)
     INV:I->O            367   0.551   3.772  reset1_INV_0 (reset)
     FDRSE:R                   1.026          cpu/writeio
d1443 2
a1444 2
    Total                      8.841ns (1.978ns logic, 6.863ns route)
                                       (22.4% logic, 77.6% route)
d1459 1
a1459 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N16300)
d1478 1
a1478 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N16300)
d1497 1
a1497 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N16300)
d1516 1
a1516 1
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N16300)
d1536 1
a1536 1
     LUT4:I1->O            3   0.551   1.246  select1/selacc426 (select1/selacc4_map5652)
d1539 4
a1542 4
     LUT4:I3->O            1   0.551   0.996  N186LogicTrst63_SW0 (N17403)
     LUT4:I1->O            1   0.551   1.140  N186LogicTrst63 (N186LogicTrst_map6210)
     LUT4:I0->O            1   0.551   0.827  N186LogicTrst126_SW0 (N17405)
     LUT4:I3->O            1   0.551   0.801  N186LogicTrst126 (data_4_IOBUF)
d1562 3
a1564 3
     LUT4:I0->O            1   0.551   0.000  _and0000_inv181 (N18091)
     MUXF5:I1->O           1   0.360   1.140  _and0000_inv18_f5 (_and0000_inv_map5862)
     LUT4:I0->O            1   0.551   1.140  _and0000_inv108 (_and0000_inv_map5889)
d1566 3
a1568 3
     LUT4:I3->O            1   0.551   1.140  N180LogicTrst120 (N180LogicTrst1_map5994)
     LUT4:I0->O           16   0.551   1.576  N180LogicTrst142 (N269)
     LUT3:I0->O            1   0.551   0.801  N194LogicTrst108 (data_0_IOBUF)
d1578 1
a1578 1
Offset:              17.289ns (Levels of Logic = 8)
d1588 7
a1594 7
     LUT4:I0->O            1   0.551   0.000  select1/selectd/selectout791 (N18071)
     MUXF5:I1->O           1   0.360   1.140  select1/selectd/selectout79_f5 (select1/selectd/selectout_map5690)
     LUT4_D:I0->O          3   0.551   0.975  select1/selectd/selectout169 (select1/selectd/selectout_map5717)
     LUT3:I2->O           17   0.551   1.371  adm3a/_and00001 (adm3a/_and0000)
     LUT4:I3->O            1   0.551   0.827  N182LogicTrst113 (N182LogicTrst_map6158)
     LUT4:I3->O            1   0.551   0.827  N182LogicTrst126_SW0 (N17397)
     LUT4:I3->O            1   0.551   0.801  N182LogicTrst126 (data_6_IOBUF)
d1597 2
a1598 2
    Total                     17.289ns (9.943ns logic, 7.346ns route)
                                       (57.5% logic, 42.5% route)
d1614 4
a1617 4
     LUT4:I0->O            1   0.551   0.000  select1/select248_SW02 (N18126)
     MUXF5:I0->O           2   0.360   1.072  select1/select248_SW0_f5 (N17258)
     LUT4:I1->O            1   0.551   0.000  select1/select2482 (N18128)
     MUXF5:I0->O           2   0.360   1.216  select1/select248_f5 (select1/select2_map5800)
d1619 2
a1620 2
     LUT4:I2->O           16   0.551   1.576  N180LogicTrst142 (N269)
     LUT3:I0->O            1   0.551   0.801  N194LogicTrst108 (data_0_IOBUF)
d1640 2
a1641 2
     LUT4:I0->O            1   0.551   0.000  select1/selectc/selectout1511 (N18101)
     MUXF5:I1->O           2   0.360   1.216  select1/selectc/selectout151_f5 (select1/selectc/selectout_map6331)
d1645 2
a1646 2
     LUT4:I3->O           16   0.551   1.576  N180LogicTrst142 (N269)
     LUT3:I0->O            1   0.551   0.801  N194LogicTrst108 (data_0_IOBUF)
d1666 6
a1671 6
     LUT4:I2->O            1   0.551   0.996  N188LogicTrst26 (N188LogicTrst_map6009)
     LUT4:I1->O            1   0.551   0.827  N188LogicTrst34 (N188LogicTrst_map6011)
     LUT4:I3->O            1   0.551   0.869  N188LogicTrst61 (N188LogicTrst_map6017)
     LUT3:I2->O            1   0.551   1.140  N188LogicTrst95_SW0 (N17625)
     LUT4:I0->O            1   0.551   0.869  N188LogicTrst95 (N188LogicTrst_map6023)
     LUT3:I2->O            1   0.551   0.801  N188LogicTrst108 (data_3_IOBUF)
d1696 1
a1696 1
CPU : 243.39 / 243.99 s | Elapsed : 243.00 / 244.00 s
d1700 1
a1700 1
Total memory usage is 241168 kilobytes
@