head 1.1; branch 1.1.1; access; symbols add:1.1.1.1 update:1.1.1.5 samiam95124:1.1.1; locks; strict; comment @# @; 1.1 date 2006.11.01.19.56.53; author samiam95124; state Exp; branches 1.1.1.1; next ; commitid 31604548faf04567; 1.1.1.1 date 2006.11.01.19.56.53; author samiam95124; state Exp; branches; next 1.1.1.2; commitid 31604548faf04567; 1.1.1.2 date 2006.11.11.12.00.14; author samiam95124; state Exp; branches; next 1.1.1.3; commitid 1fa44555b9f14567; 1.1.1.3 date 2006.11.16.10.24.20; author samiam95124; state Exp; branches; next 1.1.1.4; commitid 3f6c455c3ae54567; 1.1.1.4 date 2006.11.17.10.50.04; author samiam95124; state Exp; branches; next 1.1.1.5; commitid 3e01455d92754567; 1.1.1.5 date 2006.11.19.04.21.00; author samiam95124; state Exp; branches; next ; commitid 3554455fda5a4567; desc @@ 1.1 log @Initial revision @ text @Release 8.2.02i Map I.33 Xilinx Mapping Report File for Design 'testbench' Design Information ------------------ Command Line : C:\Xilinx\bin\nt\map.exe -ise C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf Target Device : xc3s1000 Target Package : ft256 Target Speed : -4 Mapper Version : spartan3 -- $Revision: 1.34.32.1 $ Mapped Date : Wed Nov 01 08:45:26 2006 Design Summary -------------- Number of errors: 0 Number of warnings: 9 Logic Utilization: Total Number Slice Registers: 890 out of 15,360 5% Number used as Flip Flops: 802 Number used as Latches: 88 Number of 4 input LUTs: 3,884 out of 15,360 25% Logic Distribution: Number of occupied Slices: 3,425 out of 7,680 44% Number of Slices containing only related logic: 3,425 out of 3,425 100% Number of Slices containing unrelated logic: 0 out of 3,425 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 5,760 out of 15,360 37% Number used as logic: 3,884 Number used as a route-thru: 196 Number used for Dual Port RAMs: 1,680 (Two LUTs used per Dual Port RAM) Number of bonded IOBs: 44 out of 173 25% IOB Flip Flops: 9 Number of Block RAMs: 2 out of 24 8% Number of MULT18X18s: 1 out of 24 4% Number of GCLKs: 3 out of 8 37% Total equivalent gate count for design: 278,010 Additional JTAG gate count for IOBs: 2,112 Peak Memory Usage: 194 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:LIT:243 - Logical network adm3a/display/inst_Mram_mem960/SPO has no load. WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 839 more times for the following (max. 5 shown): adm3a/display/inst_Mram_mem1100/SPO, adm3a/display/inst_Mram_mem2100/SPO, adm3a/display/inst_Mram_mem3100/SPO, adm3a/display/inst_Mram_mem4100/SPO, adm3a/display/inst_Mram_mem5100/SPO To see the details of these warning messages, please use the -detail switch. WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_clkdiv<3>/clkdiv_3_BUFG" (output signal=clkdiv<3>) has a mix of clock and non-clock loads. The non-clock loads are: Pin LI of Mcount_clkdiv_xor<3> WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed): Pin PRE of cpu/ei Pin CE of cpu/carry Pin CE of cpu/addr_0 Pin CE of cpu/addr_1 Pin CE of cpu/addr_2 WARNING:Pack:266 - The function generator adm3a/display/chradr<4>8 failed to merge with F5 multiplexer adm3a/display/chradr<5>_f5_35. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "clkdiv_3_BUFG" (output signal=clkdiv<3>), BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP), BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP) INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. Section 4 - Removed Logic Summary --------------------------------- 1 block(s) removed 3 block(s) optimized away 1 signal(s) removed Section 5 - Removed Logic ------------------------- The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logic The signal "cpu/regfil_5_1_rt1" is unused and has been removed. Unused block "cpu/regfil_5_1_rt1" (ROM) removed. Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC MUXCY cpu/Madd__AUX_12_Madd_cy<2> To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay | +------------------------------------------------------------------------------------------------------------------------+ | addr<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | b<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | b<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | b<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | clock | IOB | INPUT | LVCMOS25 | | | | | | | data<0> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD | | data<1> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD | | data<2> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD | | data<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD | | data<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD | | data<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD | | data<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD | | data<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD | | g<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | g<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | g<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | hsync_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | inta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | intr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | r<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | r<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | r<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | readio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | readmem | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | reset_n | IOB | INPUT | LVCMOS25 | | | | | | | vsync_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | waitr | IOB | INPUT | LVCMOS25 | | | | | | | writeio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | writemem | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design. Section 11 - Timing Report -------------------------- This design was not run using timing mode. Section 12 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings @ 1.1.1.1 log @8080 CPU project @ text @@ 1.1.1.2 log @8080 CPU project @ text @d13 1 a13 1 Mapped Date : Sat Nov 11 00:49:29 2006 d18 1 a18 1 Number of warnings: 10 d20 2 a21 2 Total Number Slice Registers: 683 out of 15,360 4% Number used as Flip Flops: 595 d23 1 a23 1 Number of 4 input LUTs: 4,208 out of 15,360 27% d25 3 a27 3 Number of occupied Slices: 3,312 out of 7,680 43% Number of Slices containing only related logic: 3,312 out of 3,312 100% Number of Slices containing unrelated logic: 0 out of 3,312 0% d29 3 a31 3 Total Number 4 input LUTs: 6,094 out of 15,360 39% Number used as logic: 4,208 Number used as a route-thru: 206 d34 3 a36 3 Number of bonded IOBs: 54 out of 173 31% IOB Flip Flops: 11 Number of Block RAMs: 3 out of 24 12% d38 1 a38 1 Number of GCLKs: 2 out of 8 25% d40 3 a42 3 Total equivalent gate count for design: 344,099 Additional JTAG gate count for IOBs: 2,592 Peak Memory Usage: 197 MB d92 4 d100 2 a101 2 Pin CLR of cpu/readmem Pin CLR of cpu/inta d105 2 a106 2 WARNING:Pack:266 - The function generator adm3a/display/chradr<4>81 failed to merge with F5 multiplexer adm3a/display/chradr<5>_f5_62. There is a conflict d108 1 a108 7 WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux0003. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux00071_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is d114 1 a114 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is d117 1 a117 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is d126 1 a194 8 | diag<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | diag<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | diag<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | diag<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | diag<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | diag<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | diag<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | diag<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | a200 2 | ps2_clk | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | ps2_data | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | d208 1 a208 1 | waitr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | @ 1.1.1.3 log @8080 CPU project @ text @d13 1 a13 1 Mapped Date : Wed Nov 15 08:50:16 2006 d18 1 a18 1 Number of warnings: 13 d20 2 a21 2 Total Number Slice Registers: 745 out of 15,360 4% Number used as Flip Flops: 657 d23 1 a23 1 Number of 4 input LUTs: 4,391 out of 15,360 28% d25 3 a27 3 Number of occupied Slices: 3,458 out of 7,680 45% Number of Slices containing only related logic: 3,458 out of 3,458 100% Number of Slices containing unrelated logic: 0 out of 3,458 0% d29 3 a31 3 Total Number 4 input LUTs: 6,313 out of 15,360 41% Number used as logic: 4,391 Number used as a route-thru: 242 d36 2 a37 2 Number of Block RAMs: 4 out of 24 16% Number of MULT18X18s: 2 out of 24 8% d40 1 a40 1 Total equivalent gate count for design: 415,496 d42 1 a42 1 Peak Memory Usage: 199 MB d101 2 a102 2 WARNING:Pack:266 - The function generator adm3a/display/chradr<5>35 failed to merge with F5 multiplexer adm3a/display/chradr<6>_f5_3. There is a conflict d110 1 a110 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is d116 1 a116 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is d119 1 a119 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is a121 9 WARNING:PhysDesignRules:812 - Dangling pin on block::. WARNING:PhysDesignRules:812 - Dangling pin on block::. WARNING:PhysDesignRules:812 - Dangling pin on block::. @ 1.1.1.4 log @8080 CPU project @ text @d13 1 a13 1 Mapped Date : Thu Nov 16 20:11:36 2006 d18 1 a18 1 Number of warnings: 10 d20 2 a21 2 Total Number Slice Registers: 744 out of 15,360 4% Number used as Flip Flops: 656 d23 1 a23 1 Number of 4 input LUTs: 4,397 out of 15,360 28% d25 3 a27 3 Number of occupied Slices: 3,445 out of 7,680 44% Number of Slices containing only related logic: 3,445 out of 3,445 100% Number of Slices containing unrelated logic: 0 out of 3,445 0% d29 3 a31 3 Total Number 4 input LUTs: 6,317 out of 15,360 41% Number used as logic: 4,397 Number used as a route-thru: 240 d40 1 a40 1 Total equivalent gate count for design: 415,467 d101 9 @ 1.1.1.5 log @8080 CPU project @ text @d13 1 a13 1 Mapped Date : Sat Nov 18 17:11:52 2006 d18 1 a18 1 Number of warnings: 13 d20 2 a21 2 Total Number Slice Registers: 745 out of 15,360 4% Number used as Flip Flops: 657 d23 1 a23 1 Number of 4 input LUTs: 4,379 out of 15,360 28% d25 3 a27 3 Number of occupied Slices: 3,447 out of 7,680 44% Number of Slices containing only related logic: 3,447 out of 3,447 100% Number of Slices containing unrelated logic: 0 out of 3,447 0% d29 3 a31 3 Total Number 4 input LUTs: 6,300 out of 15,360 41% Number used as logic: 4,379 Number used as a route-thru: 241 d40 1 a40 1 Total equivalent gate count for design: 415,388 a100 9 WARNING:Pack:266 - The function generator adm3a/display/chradr<5>35 failed to merge with F5 multiplexer adm3a/display/chradr<6>_f5_3. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux0007. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux00031_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. d156 1 a156 1 MUXCY cpu/Madd__AUX_13_Madd_cy<2> @