head	1.3;
access;
symbols;
locks; strict;
comment	@# @;


1.3
date	2001.10.26.20.52.26;	author khatib;	state Exp;
branches;
next	1.2;

1.2
date	2001.10.22.20.21.47;	author khatib;	state Exp;
branches;
next	1.1;

1.1
date	2001.01.26.20.54.09;	author khatib;	state Exp;
branches;
next	;


desc
@@


1.3
log
@closing flag bug fixed
@
text
@-------------------------------------------------------------------------------
-- Title      :  TX controller
-- Project    :  HDLC controller
-------------------------------------------------------------------------------
-- File        : TxCont.vhd
-- Author      : Jamil Khatib  (khatib@@ieee.org)
-- Organization: OpenIPCore Project
-- Created     :2001/01/15
-- Last update:2001/10/26
-- Platform    : 
-- Simulators  : Modelsim 5.3XE/Windows98
-- Synthesizers: 
-- Target      : 
-- Dependency  : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description:  Transmit controller
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml

-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :   15 Jan 2001
-- Modifier        :   Jamil Khatib (khatib@@ieee.org)
-- Desccription    :   Created
-- ToOptimize      :
-- Bugs            :   
-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TxCont_ent IS

  PORT (
    TXclk         : IN  STD_LOGIC;      -- TX clock
    rst_n         : IN  STD_LOGIC;      -- System Reset
    TXEN          : IN  STD_LOGIC;      -- TX enable
    enable        : OUT STD_LOGIC;      -- Enable control
    BackendEnable : OUT STD_LOGIC;      -- Backend Enable
    abortedTrans  : IN  STD_LOGIC;      -- No Valid data from the backend
    inProgress    : IN  STD_LOGIC;      -- Data in progress
    ValidFrame    : IN  STD_LOGIC;      -- Valid Frame
    Frame         : OUT STD_LOGIC;      -- Frame strobe
    AbortFrame    : IN  STD_LOGIC;      -- AbortFrame
    AbortTrans    : OUT STD_LOGIC);     -- Abort data transmission

END TxCont_ent;
-------------------------------------------------------------------------------
ARCHITECTURE TxCont_beh OF TxCont_ent IS

BEGIN  -- TxCont_beh

-- purpose: Abort Machine
-- type   : sequential
-- inputs : Txclk, rst_n
-- outputs: 
  abort_proc : PROCESS (Txclk, rst_n)

    VARIABLE counter : INTEGER RANGE 0 TO 14;  -- Counter

    VARIABLE state : STD_LOGIC;             -- Internal State
    -- state ==> '0' No abort signal
    -- state ==> '1' Abort signal
  BEGIN  -- process abort_proc
    IF rst_n = '0' THEN                     -- asynchronous reset (active low)
      AbortTrans <= '0';
      Counter    := 0;
      enable     <= '1';
      state      := '0';
    ELSIF Txclk'event AND Txclk = '1' THEN  -- rising clock edge
      IF TXEN = '1' THEN

        CASE state IS

          WHEN '0' =>
            IF abortedTrans = '1' OR AbortFrame = '1' THEN
              state    := '1';
              Counter  := 0;
            END IF;
            AbortTrans <= '0';

          WHEN '1' =>
            IF counter = 8 THEN
              counter := 0;
              IF abortedTrans = '0' AND AbortFrame = '0' THEN

                state      := '0';
                AbortTrans <= '0';
              ELSE
                AbortTrans <= '1';
              END IF;

            ELSE
              counter := counter +1;
            END IF;  -- counter

          WHEN OTHERS => NULL;

        END CASE;
      END IF;  -- TXEN
      enable <= TXEN;

    END IF;  -- TXclk
  END PROCESS abort_proc;

  -- purpose: Flag Controller 
  -- type   : sequential
  -- inputs : Txclk, rst_n
  -- outputs: 
  Flag_proc : PROCESS (Txclk, rst_n)

    VARIABLE state   : STD_LOGIC_VECTOR(2 DOWNTO 0);  -- Internal State machine
    VARIABLE counter : INTEGER RANGE 0 TO 16;         -- Internal counter

  BEGIN  -- process Flag_proc
    IF rst_n = '0' THEN                     -- asynchronous reset (active low)
      Frame         <= '0';
      state         := (OTHERS => '0');
      counter       := 0;
      BackendEnable <= '0';
    ELSIF Txclk'event AND Txclk = '1' THEN  -- rising clock edge
      IF TXEN = '1' THEN

        CASE state IS
          WHEN "000" =>                 -- Check Valid Frame
            Frame           <= '0';
            IF ValidFrame = '1' THEN
              state         := "001";
              BackendEnable <= '1';
            ELSE
              BackendEnable <= '0';
            END IF;
            counter         := 0;

          WHEN "001" =>

            IF counter > 1 AND inProgress = '0' THEN
              state := "010";
              Frame <= '1';
            ELSE
              Frame <= '0';
            END IF;

            IF inProgress = '0' THEN
              counter := counter +1;
            END IF;

            BackendEnable <= '1';

          WHEN "010" =>                 -- Check ValidFrame

            Frame <= '1';

            IF ValidFrame = '0' THEN
              state         := "011";
              BackendEnable <= '0';
            ELSE
              BackendEnable <= '1';
            END IF;

            counter := 0;

          WHEN "011" =>
            IF counter > 2 AND inProgress = '0' THEN
              state := "100";
            END IF;
            Frame   <= '1';

            IF inProgress = '0' THEN
              counter := counter +1;
            END IF;

            BackendEnable <= '0';

          WHEN "100" =>

            IF counter = 10 THEN
              counter := 0;
              state   := "000";
              Frame   <= '0';
            ELSE
              counter := counter + 1;
              Frame   <= '1';
            END IF;

            BackendEnable <= '0';

          WHEN OTHERS => NULL;
        END CASE;
      END IF;  -- TXEN
    END IF;
  END PROCESS Flag_proc;
-------------------------------------------------------------------------------
END TxCont_beh;
@


1.2
log
@Backend bug fixed
@
text
@d9 1
a9 1
-- Last update: 2001/10/20
d172 1
a172 4
              state := "000";
              Frame <= '0';
            ELSE
              Frame <= '1';
d174 1
d178 13
@


1.1
log
@Initial release (TX)
@
text
@d9 1
a9 1
-- Last update: 2001/01/26
d37 16
a52 16
library ieee;
use ieee.std_logic_1164.all;
entity TxCont_ent is

  port (
    TXclk         : in  std_logic;      -- TX clock
    rst_n         : in  std_logic;      -- System Reset
    TXEN          : in  std_logic;      -- TX enable
    enable        : out std_logic;      -- Enable control
    BackendEnable : out std_logic;      -- Backend Enable
    abortedTrans  : in  std_logic;      -- No Valid data from the backend
    inProgress    : in  std_logic;      -- Data in progress
    ValidFrame    : in  std_logic;      -- Valid Frame
    Frame         : out std_logic;      -- Frame strobe
    AbortFrame    : in  std_logic;      -- AbortFrame
    AbortTrans    : out std_logic);     -- Abort data transmission
d54 1
a54 1
end TxCont_ent;
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a56 1
architecture TxCont_beh of TxCont_ent is
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a58 1
begin  -- TxCont_beh
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  abort_proc : process (Txclk, rst_n)
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    variable counter : integer range 0 to 14;  -- Counter
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a68 1
    variable state : std_logic;             -- Internal State
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  begin  -- process abort_proc
    if rst_n = '0' then                     -- asynchronous reset (active low)
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a78 2
    elsif Txclk'event and Txclk = '1' then  -- rising clock edge
      if TXEN = '1' then
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a80 1
        case state is
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          when '0' =>
            if abortedTrans = '1' or AbortFrame = '1' then
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a86 1
            end if;
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a90 2
          when '1' =>
            if counter = 8 then
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              if abortedTrans = '0' and AbortFrame = '0' then
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a96 1
              else
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a98 1
              end if;
d100 1
a100 1
            else
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a102 1
            end if;  -- counter
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a104 1
          when others => null;
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        end case;
      end if;  -- TXEN
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a111 2
    end if;  -- TXclk
  end process abort_proc;
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a117 1
  Flag_proc : process (Txclk, rst_n)
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a120 2
    variable state   : std_logic_vector(2 downto 0);  -- Internal State machine
    variable counter : integer range 0 to 16;         -- Internal counter
d122 4
a125 4
  begin  -- process Flag_proc
    if rst_n = '0' then                 -- asynchronous reset (active low)
      Frame <= '0';
      state         := (others => '0');
d127 14
a140 12
      BackendEnable <= '1';
    elsif Txclk'event and Txclk = '1' then  -- rising clock edge
      if TXEN = '1' then

        case state is
          when "000" =>                 -- Check Valid Frame
            Frame         <= '0';
            if ValidFrame = '1' then
              state       := "001";
              counter     := 0;
            end if;
            BackendEnable <= '1';
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a142 2
          when "001" =>                 -- Wait 16 clks before set internal frame
            counter := counter + 1;
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            if counter = 16 then
              counter := 0;
d151 3
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              if inProgress = '0' then
                state     := "010";
                Frame     <= '1';
              else
                state     := "101";
                Frame     <= '0';
              end if;
            else
              Frame       <= '0';
            end if;
            BackendEnable <= '1';
a154 8
          when "101" =>                 -- Wait for inProgress

            if inProgress = '0' then
              state       := "010";
              Frame       <= '1';
            else
              Frame       <= '0';
            end if;
d157 1
a157 1
          when "010" =>                 -- Check ValidFrame
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            if ValidFrame = '0' then
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              counter       := 0;
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a164 1
            else
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a166 17
            end if;

          when "011" =>                 -- wait 16 clk before trying to unset
                                        -- internal frame
            counter   := counter + 1;
            if counter = 16 then
              counter := 0;
              if inProgress = '0' then
                state := "000";
                Frame <= '0';
              else
                state := "100";
                Frame <= '1';
              end if;
            else
              Frame <= '1';
            end if;
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a168 3
            BackendEnable <= '0';

          when "100" =>
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            if inProgress = '0' then
d174 1
a174 1
            else
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a180 1
            end if;
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          when others => null;
        end case;
      end if;  -- TXEN
    end if;
  end process Flag_proc;
d190 1
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end TxCont_beh;
@