head	1.1;
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	arelease:1.1.1.2
	avendor:1.1.1;
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1.1
date	2008.06.06.09.19.31;	author hmanske;	state Exp;
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	1.1.1.1;
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commitid	58624849010f4567;

1.1.1.1
date	2008.06.06.09.19.31;	author hmanske;	state Exp;
branches;
next	1.1.1.2;
commitid	58624849010f4567;

1.1.1.2
date	2008.06.06.10.27.07;	author hmanske;	state Exp;
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commitid	7895484910e74567;


desc
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1.1
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@Initial revision
@
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@------------------------------------------------------------------
-- PROJECT:     clvp (configurable lightweight vector processor)
--
-- ENTITY:      selectunit
--
-- PURPOSE:     selects one word out of a vector
--              register
--
-- AUTHOR:      harald manske, haraldmanske@@gmx.de
--
-- VERSION:     1.0
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

use work.cfg.all;
use work.datatypes.all;

entity selectunit is
    port (
        data_in :   in  vectordata_type;
        k_in:       in  std_logic_vector(31 downto 0);
        data_out:   out std_logic_vector(31 downto 0)
    );
end selectunit;

architecture rtl of selectunit is
    signal index: integer range 0 to k-1;
begin
   index <= conv_integer(k_in) when (k_in < k) else 0;
   data_out <= data_in(index);
end rtl;@


1.1.1.1
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1.1.1.2
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@d2 1
a2 1
-- PROJECT:    HiCoVec (highly configurable vector processor)
@