head     1.1;
branch   1.1.1;
access   ;
symbols  vlsi:1.1.1.1 marta:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2002.02.09.13.47.38;  author marta;  state Exp;
branches 1.1.1.1;
next     ;

1.1.1.1
date     2002.02.09.13.47.38;  author marta;  state Exp;
branches ;
next     ;


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1.1
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@Initial revision
@
text
@-- File Name    : fulladder.vbe
-- Description  : Full Adder in behavioral
-- Author       : Mas Adit
-- Date         : 29 Agustus 2001

ENTITY fulladder IS
PORT(
  a	: IN BIT;
  b	: IN BIT;
  cin	: IN BIT;
  sum	: OUT BIT;
  cout	: OUT BIT;
  vdd   : in  BIT;
  vss	: in  BIT
);
END fulladder;

ARCHITECTURE VBE OF fulladder IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on fulladder"
  SEVERITY WARNING;

  cout <= ((a AND b) OR (cin AND (a XOR b)));
  sum <= ((a XOR b) XOR cin);
END VBE;



@


1.1.1.1
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