head	1.2;
access;
symbols
	bg2_23:1.2
	bg2_22:1.2
	bg2_21:1.2
	bg2_20:1.2
	bg2_16:1.2
	bg2_15:1.2
	bg2_12:1.2
	bg2_07:1.2
	isorc2008_submission:1.2
	handbook_alpha_edition:1.2
	jtres2007_submission:1.2
	bg1_07:1.2
	bg1_06:1.2
	bg1_05:1.2
	TAL_101:1.2
	TAL_100:1.2
	jtres_submission:1.2
	wises06_submission:1.2
	lctes2006_submission:1.2
	rtgc_isorc2006:1.2.0.4
	isorc2006:1.2.0.2
	rtgc_paper:1.2
	bg1_00:1.2
	nohandle:1.2
	thesis:1.2
	arelease:1.1.1.1
	avendor:1.1.1;
locks; strict;
comment	@# @;


1.2
date	2004.09.16.20.00.21;	author martin;	state Exp;
branches;
next	1.1;

1.1
date	2004.02.19.13.24.42;	author martin;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2004.02.19.13.24.42;	author martin;	state Exp;
branches;
next	;


desc
@@


1.2
log
@bytecode load in hardware (mem32.vhd).
@
text
@--Copyright (C) 1991-2004 Altera Corporation
--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--support information,  device programming or simulation file,  and any other
--associated  documentation or information  provided by  Altera  or a partner
--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--other  use  of such  megafunction  design,  netlist,  support  information,
--device programming or simulation file,  or any other  related documentation
--or information  is prohibited  for  any  other purpose,  including, but not
--limited to  modification,  reverse engineering,  de-compiling, or use  with
--any other  silicon devices,  unless such use is  explicitly  licensed under
--a separate agreement with  Altera  or a megafunction partner.  Title to the
--intellectual property,  including patents,  copyrights,  trademarks,  trade
--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--support  information,  device programming or simulation file,  or any other
--related documentation or information provided by  Altera  or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.


component pll
	PORT
	(
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC 
	);
end component;
@


1.1
log
@Initial revision
@
text
@d1 1
a1 1
--Copyright (C) 1991-2003 Altera Corporation
@


1.1.1.1
log
@initial cvs import.
@
text
@@