head	1.14;
access;
symbols
	bg2_23:1.14
	bg2_22:1.13
	bg2_21:1.13
	bg2_20:1.13
	bg2_16:1.13
	bg2_15:1.13
	bg2_12:1.13
	bg2_07:1.13
	isorc2008_submission:1.4
	handbook_alpha_edition:1.3
	jtres2007_submission:1.3;
locks; strict;
comment	@# @;


1.14
date	2008.08.07.16.08.05;	author 9914pich;	state Exp;
branches;
next	1.13;
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1.13
date	2008.03.04.23.39.43;	author martin;	state Exp;
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date	2008.03.04.19.19.43;	author martin;	state Exp;
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1.11
date	2008.03.04.19.01.55;	author martin;	state Exp;
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date	2008.03.03.09.45.43;	author martin;	state Exp;
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1.9
date	2008.02.23.23.18.43;	author martin;	state Exp;
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date	2008.02.20.15.46.58;	author martin;	state Exp;
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date	2008.02.19.10.19.27;	author jeuneS2;	state Exp;
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1.4
date	2007.12.02.15.36.08;	author martin;	state Exp;
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date	2007.04.14.18.38.09;	author martin;	state Exp;
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desc
@@


1.14
log
@Added mux_mem and is_pipelined to the sensitivity list
@
text
@--
--
--  This file is a part of JOP, the Java Optimized Processor
--
--  Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com)
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--


--
--	jopcpu.vhd
--
--	The JOP CPU
--
--	2007-03-16	creation
--	2007-04-13	Changed memory connection to records
--	2008-02-20	memory - I/O muxing after the memory controller (mem_sc)
--	2008-03-03	added scratchpad RAM
--	2008-03-04	correct MUX selection
--
--	todo: clean up: substitute all signals by records


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.jop_types.all;
use work.sc_pack.all;


entity jopcpu is

generic (
	jpc_width	: integer;			-- address bits of java bytecode pc = cache size
	block_bits	: integer;			-- 2*block_bits is number of cache blocks
	spm_width	: integer := 0		-- size of scratchpad RAM (in number of address bits)
);

port (
	clk		: in std_logic;
	reset	: in std_logic;

--
--	SimpCon memory interface
--
	sc_mem_out		: out sc_out_type;
	sc_mem_in		: in sc_in_type;

--
--	SimpCon IO interface
--
	sc_io_out		: out sc_out_type;
	sc_io_in		: in sc_in_type;

--
--	Interrupts from sc_sys
--
	irq_in			: in irq_bcf_type;
	irq_out			: out irq_ack_type;
	exc_req			: out exception_type
);
end jopcpu;

architecture rtl of jopcpu is

--
--	Signals
--

	signal stack_tos		: std_logic_vector(31 downto 0);
	signal stack_nos		: std_logic_vector(31 downto 0);
	signal rd, wr			: std_logic;
	signal ext_addr			: std_logic_vector(EXTA_WIDTH-1 downto 0);
	signal stack_din		: std_logic_vector(31 downto 0);

-- extension/mem interface

	signal mem_in			: mem_in_type;
	signal mem_out			: mem_out_type;

	signal sc_ctrl_mem_out	: sc_out_type;
	signal sc_ctrl_mem_in	: sc_in_type;

	signal sc_scratch_out	: sc_out_type;
	signal sc_scratch_in	: sc_in_type;

	signal next_mux_mem		: std_logic_vector(1 downto 0);
	signal dly_mux_mem		: std_logic_vector(1 downto 0);
	signal mux_mem			: std_logic_vector(1 downto 0);
	signal is_pipelined		: std_logic;

	signal mem_access		: std_logic;
	signal scratch_access	: std_logic;
	signal io_access		: std_logic;

	signal bsy				: std_logic;

	signal jbc_addr			: std_logic_vector(jpc_width-1 downto 0);
	signal jbc_data			: std_logic_vector(7 downto 0);

-- SimpCon io interface

	signal sp_ov			: std_logic;

begin

--
--	components of jop
--

	cmp_core: entity work.core
		generic map(jpc_width)
		port map (clk, reset,
			bsy,
			stack_din, ext_addr,
			rd, wr,
			jbc_addr, jbc_data,
			irq_in, irq_out, sp_ov,
			stack_tos, stack_nos
		);

	exc_req.spov <= sp_ov;

	cmp_ext: entity work.extension 
		port map (
			clk => clk,
			reset => reset,
			ain => stack_tos,
			bin => stack_nos,

			ext_addr => ext_addr,
			rd => rd,
			wr => wr,
			bsy => bsy,
			dout => stack_din,

			mem_in => mem_in,
			mem_out => mem_out
		);

	cmp_mem: entity work.mem_sc
		generic map (
			jpc_width => jpc_width,
			block_bits => block_bits
		)
		port map (
			clk => clk,
			reset => reset,
			ain => stack_tos,
			bin => stack_nos,

			np_exc => exc_req.np,
			ab_exc => exc_req.ab,

			mem_in => mem_in,
			mem_out => mem_out,
	
			jbc_addr => jbc_addr,
			jbc_data => jbc_data,

			sc_mem_out => sc_ctrl_mem_out,
			sc_mem_in => sc_ctrl_mem_in
		);


	--
	-- Generate scratchpad memory when size is != 0.
	-- Results in warnings when the size is 0.
	--
	sc1: if spm_width /= 0 generate
		cmp_scm: entity work.sdpram
			generic map (
				width => 32,
				addr_width => spm_width
			)
			port map (
				wrclk => clk,
				data => sc_scratch_out.wr_data,
				wraddress => sc_scratch_out.address(spm_width-1 downto 0),
				wren => sc_scratch_out.wr,
				rdclk => clk,
				rdaddress => sc_scratch_out.address(spm_width-1 downto 0),
				rden => sc_scratch_out.rd,
				dout => sc_scratch_in.rd_data
		);
	end generate;

	sc_scratch_in.rdy_cnt <= (others => '0');

	--
	--	Select for the read mux
	--
	--	TODO: this mux selection works ONLY for two cycle pipelining!
	--

process(clk, reset)
begin
	if (reset='1') then
		dly_mux_mem <= (others => '0');
		next_mux_mem <= (others => '0');
		is_pipelined <= '0';
	elsif rising_edge(clk) then

		if sc_ctrl_mem_out.rd='1' or sc_ctrl_mem_out.wr='1' then
			-- highest address bits decides between IO, memory, and on-chip memory
			-- save the mux selection on read or write
			next_mux_mem <= sc_ctrl_mem_out.address(SC_ADDR_SIZE-1 downto SC_ADDR_SIZE-2);
			-- a read or write with rdy_cnt of 1 means pipelining
			if sc_ctrl_mem_in.rdy_cnt(1) = '0' then
				is_pipelined <= '1';
			end if;
		end if;
		-- delayed mux selection for pipelined access
		if sc_ctrl_mem_in.rdy_cnt(1) = '0' then
			dly_mux_mem <= next_mux_mem;
		end if;
		-- pipelining is over
		if sc_ctrl_mem_in.rdy_cnt = "00" then
			is_pipelined <= '0';
		end if;

	end if;
end process;

process(next_mux_mem, dly_mux_mem, sc_ctrl_mem_out, sc_ctrl_mem_in, sc_mem_in, sc_io_in, sc_scratch_in, is_pipelined, mux_mem)
begin

	mem_access <= '0';
	scratch_access <= '0';
	io_access <= '0';

	-- for one cycle peripherals we need to set the mux from next_mux_mem
	mux_mem <= next_mux_mem;
	-- for pipelining we need to delay the mux selection
	if is_pipelined='1' then
		mux_mem <= dly_mux_mem;
	end if;

	-- read MUX
	case mux_mem is
		when "10" =>
			sc_ctrl_mem_in <= sc_scratch_in;
		when "11" =>
			sc_ctrl_mem_in <= sc_io_in;
		when others =>
			sc_ctrl_mem_in <= sc_mem_in;
	end case;

	-- select
	case sc_ctrl_mem_out.address(SC_ADDR_SIZE-1 downto SC_ADDR_SIZE-2) is
		when "10" =>
			scratch_access <= '1';
		when "11" =>
			io_access <= '1';
		when others =>
			mem_access <= '1';
	end case;

end process;

	sc_mem_out.address <= sc_ctrl_mem_out.address;
	sc_mem_out.wr_data <= sc_ctrl_mem_out.wr_data;
	sc_mem_out.wr <= sc_ctrl_mem_out.wr and mem_access;
	sc_mem_out.rd <= sc_ctrl_mem_out.rd and mem_access;

	sc_scratch_out.address <= sc_ctrl_mem_out.address;
	sc_scratch_out.wr_data <= sc_ctrl_mem_out.wr_data;
	sc_scratch_out.wr <= sc_ctrl_mem_out.wr and scratch_access;
	sc_scratch_out.rd <= sc_ctrl_mem_out.rd and scratch_access;

	sc_io_out.address <= sc_ctrl_mem_out.address;
	sc_io_out.wr_data <= sc_ctrl_mem_out.wr_data;
	sc_io_out.wr <= sc_ctrl_mem_out.wr and io_access;
	sc_io_out.rd <= sc_ctrl_mem_out.rd and io_access;

end rtl;
@


1.13
log
@correction for pipelined mux selection
@
text
@d238 1
a238 1
process(next_mux_mem, dly_mux_mem, sc_ctrl_mem_out, sc_ctrl_mem_in, sc_mem_in, sc_io_in, sc_scratch_in)
@


1.12
log
@corrected MUX selection of SimpCon slaves (mem, scratchpad, IO)
@
text
@d101 1
d103 2
d212 1
a212 1
		mux_mem <= (others => '0');
d214 1
d221 4
d226 1
a226 1
		-- take the mux selection over for the next cycle
d228 5
a232 1
			mux_mem <= next_mux_mem;
d234 1
d238 1
a238 1
process(mux_mem, sc_ctrl_mem_out, sc_ctrl_mem_in, sc_mem_in, sc_io_in, sc_scratch_in)
d245 7
@


1.11
log
@correct error in MUX selection
@
text
@d31 1
@


1.10
log
@added scratchpad RAM
@
text
@d99 1
d202 2
d209 1
d214 6
a219 1
			mux_mem <= sc_ctrl_mem_out.address(SC_ADDR_SIZE-1 downto SC_ADDR_SIZE-2);
@


1.9
log
@JOP goes GPL
@
text
@d30 1
d47 2
a48 1
	block_bits	: integer			-- 2*block_bits is number of cache blocks
d96 4
a99 1
	signal mux_mem			: std_logic;
d101 2
d175 25
a199 1
	--	Select and mux for memory and IO
d205 1
a205 1
		mux_mem <= '0';
d209 2
a210 6
			-- highest address bit decides between IO and memory
			if sc_ctrl_mem_out.address(SC_ADDR_SIZE-1)='0' then
				mux_mem <= '1';
			else
				mux_mem <= '0';
			end if;
d215 1
a215 1
process(mux_mem, sc_ctrl_mem_out, sc_ctrl_mem_in, sc_mem_in, sc_io_in)
d218 23
a240 6
	sc_ctrl_mem_in <= sc_mem_in;
	mem_access <= '1';

	if mux_mem='0' then
		sc_ctrl_mem_in <= sc_io_in;
	end if;
a241 3
	if sc_ctrl_mem_out.address(SC_ADDR_SIZE-1)='1' then
		mem_access <= '0';
	end if;
d249 5
d256 2
a257 2
	sc_io_out.wr <= sc_ctrl_mem_out.wr and not mem_access;
	sc_io_out.rd <= sc_ctrl_mem_out.rd and not mem_access;
@


1.8
log
@Moved IO/memory muxing after the memory controller
@
text
@d2 21
@


1.7
log
@Moved IO/memory muxing after the memory controller
@
text
@d8 1
@


1.6
log
@Cleanup of SimpCon types
@
text
@d69 6
d117 1
a117 4
			mem_out => mem_out,
	
			sc_io_out => sc_io_out,
			sc_io_in => sc_io_in
d140 2
a141 2
			sc_mem_out => sc_mem_out,
			sc_mem_in => sc_mem_in
d144 47
@


1.5
log
@Changes for getfield/putfield in hardware.
@
text
@d34 1
a34 1
	sc_mem_out		: out sc_mem_out_type;
d40 1
a40 1
	sc_io_out		: out sc_io_out_type;
@


1.4
log
@additional signal from bcfetch to sc_sys (int ack)
@
text
@a53 2
	constant EXTA_WIDTH : integer := 3;

a97 1
		generic map (exta_width => EXTA_WIDTH)
@


1.3
log
@Hardware implementation of iaload and iastore
@
text
@d44 1
a44 1
--	Interrupts from IO devices
d46 2
a47 1
	irq_in			: in irq_in_type;
d93 1
a93 1
			irq_in, sp_ov,
@


1.2
log
@Constants for ext_addr encoding, records for extension/mem interface
@
text
@d127 5
a131 1
			din => stack_tos,
@


1.1
log
@changed the structure of JOP with additional jopcpu between top-level and core
@
text
@d7 1
d67 3
a69 7
	signal mem_rd			: std_logic;
	signal mem_wr			: std_logic;
	signal mem_addr_wr		: std_logic;
	signal mem_bc_rd		: std_logic;
	signal mem_dout			: std_logic_vector(31 downto 0);
	signal mem_bcstart		: std_logic_vector(31 downto 0);
	signal mem_bsy			: std_logic;
a74 10
-- memory interface

	signal ram_addr			: std_logic_vector(17 downto 0);
	signal ram_dout			: std_logic_vector(31 downto 0);
	signal ram_din			: std_logic_vector(31 downto 0);
	signal ram_dout_en		: std_logic;
	signal ram_ncs			: std_logic;
	signal ram_noe			: std_logic;
	signal ram_nwe			: std_logic;

d112 2
a113 7
			mem_rd => mem_rd,
			mem_wr => mem_wr,
			mem_addr_wr => mem_addr_wr,
			mem_bc_rd => mem_bc_rd,
			mem_data => mem_dout,
			mem_bcstart => mem_bcstart,
			mem_bsy => mem_bsy,
d122 1
a122 2
			block_bits => block_bits,
			addr_bits => 21
d129 3
a131 8
			mem_rd => mem_rd,
			mem_wr => mem_wr,
			mem_addr_wr => mem_addr_wr,
			mem_bc_rd => mem_bc_rd,
			dout => mem_dout,
			bcstart => mem_bcstart,
			bsy => mem_bsy,

d135 2
a136 6
			address => sc_mem_out.address,
			wr_data => sc_mem_out.wr_data,
			rd => sc_mem_out.rd,
			wr => sc_mem_out.wr,
			rd_data => sc_mem_in.rd_data,
			rdy_cnt => sc_mem_in.rdy_cnt
@