head	1.2;
access;
symbols
	rel_13:1.1
	rel_12:1.1
	rel_11:1.1
	rel_10:1.1
	rel_9:1.1
	rel_8:1.1
	rel_WB_B3:1.1
	rel_7:1.1
	rel_6:1.1
	rel_4:1.1
	rel_2:1.1
	rel_00:1.1;
locks; strict;
comment	@# @;


1.2
date	2004.08.19.15.27.39;	author mihad;	state Exp;
branches;
next	1.1;

1.1
date	2002.02.19.17.07.31;	author mihad;	state Exp;
branches;
next	;


desc
@@


1.2
log
@Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.
@
text
@ncvlog: 05.10-s012: (c) Copyright 1995-2004 Cadence Design Systems, Inc.
TOOL:	ncvlog	05.10-s012: Started on Aug 19, 2004 at 17:13:31
ncvlog
    -f ./ncvlog.args
        -cdslib ../bin/cds.lib
        -hdlvar ../bin/hdl.var
        -logfile ../log/ncvlog.log
        -update
        -messages
        -INCDIR ../../../bench/verilog
        -INCDIR ../../../rtl/verilog
        -DEFINE PCI_CPCI_SIM
        ../../../rtl/verilog/pci_spoci_ctrl.v
        ../../../rtl/verilog/pci_parity_check.v
        ../../../rtl/verilog/pci_target_unit.v
        ../../../rtl/verilog/pci_wb_addr_mux.v
        ../../../rtl/verilog/pci_cbe_en_crit.v
        ../../../rtl/verilog/pci_pcir_fifo_control.v
        ../../../rtl/verilog/pci_out_reg.v
        ../../../rtl/verilog/pci_pci_tpram.v
        ../../../rtl/verilog/pci_wb_master.v
        ../../../rtl/verilog/pci_conf_cyc_addr_dec.v
        ../../../rtl/verilog/pci_frame_crit.v
        ../../../rtl/verilog/pci_target32_clk_en.v
        ../../../rtl/verilog/pci_pciw_fifo_control.v
        ../../../rtl/verilog/pci_wb_slave.v
        ../../../rtl/verilog/pci_conf_space.v
        ../../../rtl/verilog/pci_frame_en_crit.v
        ../../../rtl/verilog/pci_par_crit.v
        ../../../rtl/verilog/pci_pciw_pcir_fifos.v
        ../../../rtl/verilog/pci_wb_slave_unit.v
        ../../../rtl/verilog/pci_frame_load_crit.v
        ../../../rtl/verilog/pci_bridge32.v
        ../../../rtl/verilog/pci_target32_devs_crit.v
        ../../../rtl/verilog/pci_perr_crit.v
        ../../../rtl/verilog/pci_wbr_fifo_control.v
        ../../../rtl/verilog/pci_cur_out_reg.v
        ../../../rtl/verilog/pci_pci_decoder.v
        ../../../rtl/verilog/pci_target32_interface.v
        ../../../rtl/verilog/pci_perr_en_crit.v
        ../../../rtl/verilog/pci_wbw_fifo_control.v
        ../../../rtl/verilog/pci_wb_decoder.v
        ../../../rtl/verilog/pci_in_reg.v
        ../../../rtl/verilog/pci_serr_crit.v
        ../../../rtl/verilog/pci_wbw_wbr_fifos.v
        ../../../rtl/verilog/pci_delayed_sync.v
        ../../../rtl/verilog/pci_irdy_out_crit.v
        ../../../rtl/verilog/pci_io_mux.v
        ../../../rtl/verilog/pci_io_mux_ad_en_crit.v
        ../../../rtl/verilog/pci_io_mux_ad_load_crit.v
        ../../../rtl/verilog/pci_target32_sm.v
        ../../../rtl/verilog/pci_serr_en_crit.v
        ../../../rtl/verilog/pci_delayed_write_reg.v
        ../../../rtl/verilog/pci_mas_ad_en_crit.v
        ../../../rtl/verilog/pci_mas_ad_load_crit.v
        ../../../rtl/verilog/pci_master32_sm.v
        ../../../rtl/verilog/pci_target32_stop_crit.v
        ../../../rtl/verilog/pci_synchronizer_flop.v
        ../../../rtl/verilog/pci_async_reset_flop.v
        ../../../rtl/verilog/pci_mas_ch_state_crit.v
        ../../../rtl/verilog/pci_master32_sm_if.v
        ../../../rtl/verilog/pci_target32_trdy_crit.v
        ../../../rtl/verilog/pci_rst_int.v
        ../../../rtl/verilog/pci_sync_module.v
        ../../../rtl/verilog/pci_wb_tpram.v
        ../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v
        ../../../bench/verilog/top.v
        ../../../bench/verilog/wb_master32.v
        ../../../bench/verilog/wb_master_behavioral.v
        ../../../bench/verilog/system.v
        ../../../bench/verilog/pci_blue_arbiter.v
        ../../../bench/verilog/pci_bus_monitor.v
        ../../../bench/verilog/pci_behaviorial_device.v
        ../../../bench/verilog/pci_behaviorial_master.v
        ../../../bench/verilog/pci_behaviorial_target.v
        ../../../bench/verilog/wb_slave_behavioral.v
        ../../../bench/verilog/wb_bus_mon.v
        ../../../bench/verilog/pci_unsupported_commands_master.v
        ../../../bench/verilog/pci_behavioral_pci2pci_bridge.v
        ../../../bench/verilog/i2c_slave_model.v

file: ../../../rtl/verilog/pci_spoci_ctrl.v
	module worklib.pci_spoci_ctrl
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_parity_check.v
	module worklib.pci_parity_check
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target_unit.v
	module worklib.pci_target_unit
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_wb_addr_mux.v
	module worklib.pci_wb_addr_mux
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_cbe_en_crit.v
file: ../../../rtl/verilog/pci_pcir_fifo_control.v
	module worklib.pci_pcir_fifo_control
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_out_reg.v
	module worklib.pci_out_reg
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_pci_tpram.v
	module worklib.pci_pci_tpram
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_wb_master.v
	module worklib.pci_wb_master
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_conf_cyc_addr_dec.v
file: ../../../rtl/verilog/pci_frame_crit.v
file: ../../../rtl/verilog/pci_target32_clk_en.v
file: ../../../rtl/verilog/pci_pciw_fifo_control.v
	module worklib.pci_pciw_fifo_control
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_wb_slave.v
	module worklib.pci_wb_slave
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_conf_space.v
	module worklib.pci_conf_space
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_frame_en_crit.v
file: ../../../rtl/verilog/pci_par_crit.v
file: ../../../rtl/verilog/pci_pciw_pcir_fifos.v
	module worklib.pci_pciw_pcir_fifos
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_wb_slave_unit.v
	module worklib.pci_wb_slave_unit
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_frame_load_crit.v
file: ../../../rtl/verilog/pci_bridge32.v
	module worklib.pci_bridge32
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_devs_crit.v
file: ../../../rtl/verilog/pci_perr_crit.v
file: ../../../rtl/verilog/pci_wbr_fifo_control.v
	module worklib.pci_wbr_fifo_control
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_cur_out_reg.v
	module worklib.pci_cur_out_reg
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_pci_decoder.v
	module worklib.pci_pci_decoder
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_interface.v
	module worklib.pci_target32_interface
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_perr_en_crit.v
file: ../../../rtl/verilog/pci_wbw_fifo_control.v
	module worklib.pci_wbw_fifo_control
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_wb_decoder.v
	module worklib.pci_wb_decoder
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_in_reg.v
	module worklib.pci_in_reg
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_serr_crit.v
file: ../../../rtl/verilog/pci_wbw_wbr_fifos.v
	module worklib.pci_wbw_wbr_fifos
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_delayed_sync.v
	module worklib.pci_delayed_sync
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_irdy_out_crit.v
file: ../../../rtl/verilog/pci_io_mux.v
file: ../../../rtl/verilog/pci_io_mux_ad_en_crit.v
file: ../../../rtl/verilog/pci_io_mux_ad_load_crit.v
file: ../../../rtl/verilog/pci_target32_sm.v
	module worklib.pci_target32_sm
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_serr_en_crit.v
file: ../../../rtl/verilog/pci_delayed_write_reg.v
	module worklib.pci_delayed_write_reg
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_mas_ad_en_crit.v
file: ../../../rtl/verilog/pci_mas_ad_load_crit.v
file: ../../../rtl/verilog/pci_master32_sm.v
	module worklib.pci_master32_sm
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_stop_crit.v
file: ../../../rtl/verilog/pci_synchronizer_flop.v
file: ../../../rtl/verilog/pci_async_reset_flop.v
	module worklib.pci_async_reset_flop
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_mas_ch_state_crit.v
file: ../../../rtl/verilog/pci_master32_sm_if.v
	module worklib.pci_master32_sm_if
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_trdy_crit.v
file: ../../../rtl/verilog/pci_rst_int.v
	module worklib.pci_rst_int
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_sync_module.v
file: ../../../rtl/verilog/pci_wb_tpram.v
	module worklib.pci_wb_tpram
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v
	module worklib.pci_wbs_wbb3_2_wbb2
		errors: 0, warnings: 0
file: ../../../bench/verilog/top.v
	module worklib.TOP
		errors: 0, warnings: 0
file: ../../../bench/verilog/wb_master32.v
	module worklib.WB_MASTER32
		errors: 0, warnings: 0
file: ../../../bench/verilog/wb_master_behavioral.v
	module worklib.WB_MASTER_BEHAVIORAL
		errors: 0, warnings: 0
file: ../../../bench/verilog/system.v
	module worklib.SYSTEM
		errors: 0, warnings: 0
file: ../../../bench/verilog/pci_blue_arbiter.v
file: ../../../bench/verilog/pci_bus_monitor.v
file: ../../../bench/verilog/pci_behaviorial_device.v
file: ../../../bench/verilog/pci_behaviorial_master.v
file: ../../../bench/verilog/pci_behaviorial_target.v
file: ../../../bench/verilog/wb_slave_behavioral.v
	module worklib.WB_SLAVE_BEHAVIORAL
		errors: 0, warnings: 0
file: ../../../bench/verilog/wb_bus_mon.v
	module worklib.WB_BUS_MON
		errors: 0, warnings: 0
file: ../../../bench/verilog/pci_unsupported_commands_master.v
	module worklib.pci_unsupported_commands_master
		errors: 0, warnings: 0
file: ../../../bench/verilog/pci_behavioral_pci2pci_bridge.v
	module worklib.pci_behavioral_pci2pci_bridge
		errors: 0, warnings: 0
file: ../../../bench/verilog/i2c_slave_model.v
TOOL:	ncvlog	05.10-s012: Exiting on Aug 19, 2004 at 17:13:32  (total: 00:00:01)
@


1.1
log
@Modified testbench and fixed some bugs
@
text
@d1 2
a2 2
ncvlog: v03.30.(p001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
ncvlog: v03.30.(p001): Started on Jul 08, 2001 at 11:28:41
d12 2
d16 8
a23 8
        ../../../rtl/verilog/wb_addr_mux.v
        ../../../rtl/verilog/cbe_en_crit.v
        ../../../rtl/verilog/fifo_control.v
        ../../../rtl/verilog/out_reg.v
        ../../../rtl/verilog/pci_tpram.v
        ../../../rtl/verilog/wb_master.v
        ../../../rtl/verilog/conf_cyc_addr_dec.v
        ../../../rtl/verilog/frame_crit.v
d25 8
a32 8
        ../../../rtl/verilog/pciw_fifo_control.v
        ../../../rtl/verilog/wb_slave.v
        ../../../rtl/verilog/conf_space.v
        ../../../rtl/verilog/frame_en_crit.v
        ../../../rtl/verilog/par_crit.v
        ../../../rtl/verilog/pciw_pcir_fifos.v
        ../../../rtl/verilog/wb_slave_unit.v
        ../../../rtl/verilog/frame_load_crit.v
d35 4
a38 4
        ../../../rtl/verilog/perr_crit.v
        ../../../rtl/verilog/wbr_fifo_control.v
        ../../../rtl/verilog/cur_out_reg.v
        ../../../rtl/verilog/pci_decoder.v
d40 3
a42 3
        ../../../rtl/verilog/perr_en_crit.v
        ../../../rtl/verilog/wbw_fifo_control.v
        ../../../rtl/verilog/decoder.v
d44 4
a47 4
        ../../../rtl/verilog/serr_crit.v
        ../../../rtl/verilog/wbw_wbr_fifos.v
        ../../../rtl/verilog/delayed_sync.v
        ../../../rtl/verilog/irdy_out_crit.v
d52 4
a55 4
        ../../../rtl/verilog/serr_en_crit.v
        ../../../rtl/verilog/delayed_write_reg.v
        ../../../rtl/verilog/mas_ad_en_crit.v
        ../../../rtl/verilog/mas_ad_load_crit.v
d58 3
a60 3
        ../../../rtl/verilog/synchronizer_flop.v
        ../../../rtl/verilog/async_reset_flop.v
        ../../../rtl/verilog/mas_ch_state_crit.v
a62 1
        ../../../rtl/verilog/top.v
d64 4
a67 2
        ../../../rtl/verilog/sync_module.v
        ../../../rtl/verilog/wb_tpram.v
a77 1
        ../../../bench/verilog/pci_behavioral_iack_target.v
d79 2
a80 3
        ../../../../../../lib/xilinx/lib/glbl/glbl.v
        ../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
        ../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
d82 3
d86 1
a86 1
	module worklib.PCI_PARITY_CHECK:v
d89 1
a89 7
	module worklib.PCI_TARGET_UNIT:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/wb_addr_mux.v
	module worklib.WB_ADDR_MUX:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/cbe_en_crit.v
	module worklib.CBE_EN_CRIT:v (up-to-date)
d91 2
a92 2
file: ../../../rtl/verilog/fifo_control.v
	module worklib.FIFO_CONTROL:v
d94 3
a96 2
file: ../../../rtl/verilog/out_reg.v
	module worklib.OUT_REG:v
d98 2
a99 2
file: ../../../rtl/verilog/pci_tpram.v
	module worklib.PCI_TPRAM:v
d101 2
a102 2
file: ../../../rtl/verilog/wb_master.v
	module worklib.WB_MASTER:v
d104 2
a105 5
file: ../../../rtl/verilog/conf_cyc_addr_dec.v
	module worklib.CONF_CYC_ADDR_DEC:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/frame_crit.v
	module worklib.FRAME_CRIT:v (up-to-date)
d107 2
d110 2
a111 4
	module worklib.PCI_TARGET32_CLK_EN:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pciw_fifo_control.v
	module worklib.PCIW_FIFO_CONTROL:v
d113 2
a114 2
file: ../../../rtl/verilog/wb_slave.v
	module worklib.WB_SLAVE:v
d116 2
a117 2
file: ../../../rtl/verilog/conf_space.v
	module worklib.CONF_SPACE:v
d119 4
a122 2
file: ../../../rtl/verilog/frame_en_crit.v
	module worklib.FRAME_EN_CRIT:v (up-to-date)
d124 2
a125 11
file: ../../../rtl/verilog/par_crit.v
	module worklib.PAR_CRIT:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pciw_pcir_fifos.v
	module worklib.PCIW_PCIR_FIFOS:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/wb_slave_unit.v
	module worklib.WB_SLAVE_UNIT:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/frame_load_crit.v
	module worklib.FRAME_LOAD_CRIT:v (up-to-date)
d127 1
d129 1
a129 1
	module worklib.PCI_BRIDGE32:v
d132 3
a134 4
	module worklib.PCI_TARGET32_DEVS_CRIT:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/perr_crit.v
	module worklib.PERR_CRIT:v (up-to-date)
d136 2
a137 2
file: ../../../rtl/verilog/wbr_fifo_control.v
	module worklib.WBR_FIFO_CONTROL:v
d139 2
a140 5
file: ../../../rtl/verilog/cur_out_reg.v
	module worklib.CUR_OUT_REG:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_decoder.v
	module worklib.PCI_DECODER:v
d143 1
a143 4
	module worklib.PCI_TARGET32_INTERFACE:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/perr_en_crit.v
	module worklib.PERR_EN_CRIT:v (up-to-date)
d145 3
a147 2
file: ../../../rtl/verilog/wbw_fifo_control.v
	module worklib.WBW_FIFO_CONTROL:v
d149 2
a150 2
file: ../../../rtl/verilog/decoder.v
	module worklib.DECODER:v
d153 1
a153 7
	module worklib.PCI_IN_REG:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/serr_crit.v
	module worklib.SERR_CRIT:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/wbw_wbr_fifos.v
	module worklib.WBW_WBR_FIFOS:v
d155 3
a157 2
file: ../../../rtl/verilog/delayed_sync.v
	module worklib.DELAYED_SYNC:v
d159 2
a160 2
file: ../../../rtl/verilog/irdy_out_crit.v
	module worklib.IRDY_OUT_CRIT:v (up-to-date)
d162 1
a163 2
	module worklib.PCI_IO_MUX:v (up-to-date)
		errors: 0, warnings: 0
a164 2
	module worklib.PCI_IO_MUX_AD_EN_CRIT:v (up-to-date)
		errors: 0, warnings: 0
a165 2
	module worklib.PCI_IO_MUX_AD_LOAD_CRIT:v (up-to-date)
		errors: 0, warnings: 0
d167 1
a167 4
	module worklib.PCI_TARGET32_SM:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/serr_en_crit.v
	module worklib.SERR_EN_CRIT:v (up-to-date)
d169 3
a171 8
file: ../../../rtl/verilog/delayed_write_reg.v
	module worklib.DELAYED_WRITE_REG:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/mas_ad_en_crit.v
	module worklib.MAS_AD_EN_CRIT:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/mas_ad_load_crit.v
	module worklib.MAS_AD_LOAD_CRIT:v (up-to-date)
d173 2
d176 1
a176 1
	module worklib.PCI_MASTER32_SM:v
d179 3
a181 10
	module worklib.PCI_TARGET32_STOP_CRIT:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/synchronizer_flop.v
	module worklib.synchronizer_flop:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/async_reset_flop.v
	module worklib.async_reset_flop:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/mas_ch_state_crit.v
	module worklib.MAS_CH_STATE_CRIT:v (up-to-date)
d183 1
d185 1
a185 1
	module worklib.PCI_MASTER32_SM_IF:v
d188 2
a189 4
	module worklib.PCI_TARGET32_TRDY_CRIT:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../rtl/verilog/top.v
	module worklib.TOP:v
d191 3
a193 2
file: ../../../rtl/verilog/pci_rst_int.v
	module worklib.PCI_RST_INT:v
d195 2
a196 2
file: ../../../rtl/verilog/sync_module.v
	module worklib.SYNC_MODULE:v (up-to-date)
d198 2
a199 2
file: ../../../rtl/verilog/wb_tpram.v
	module worklib.WB_TPRAM:v
d202 1
a202 1
	module worklib.WB_MASTER32:v
d205 1
a205 1
	module worklib.WB_MASTER_BEHAVIORAL:v
d208 1
a208 1
	module worklib.SYSTEM:v
a210 2
	module worklib.pci_blue_arbiter:v (up-to-date)
		errors: 0, warnings: 0
a211 2
	module worklib.pci_bus_monitor:v (up-to-date)
		errors: 0, warnings: 0
a212 4
	module worklib.pci_behaviorial_device:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.delayed_test_pad:v (up-to-date)
		errors: 0, warnings: 0
a213 2
	module worklib.pci_behaviorial_master:v (up-to-date)
		errors: 0, warnings: 0
a214 2
	module worklib.pci_behaviorial_target:v (up-to-date)
		errors: 0, warnings: 0
d216 1
a216 1
	module worklib.WB_SLAVE_BEHAVIORAL:v
d219 1
a219 4
	module worklib.WB_BUS_MON:v
		errors: 0, warnings: 0
file: ../../../bench/verilog/pci_behavioral_iack_target.v
	module worklib.PCI_BEHAVIORAL_IACK_TARGET:v
d222 1
a222 7
	module worklib.pci_unsupported_commands_master:v
		errors: 0, warnings: 0
file: ../../../../../../lib/xilinx/lib/glbl/glbl.v
	module worklib.glbl:v (up-to-date)
		errors: 0, warnings: 0
file: ../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
	module worklib.RAMB4_S16_S16:v (up-to-date)
d224 2
a225 2
file: ../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
	module worklib.RAM16X1D:v (up-to-date)
d227 2
a228 1
ncvlog: v03.30.(p001): Exiting on Jul 08, 2001 at 11:28:46  (total: 00:00:05)
@