head	1.1;
access;
symbols;
locks; strict;
comment	@# @;


1.1
date	2007.02.07.08.09.19;	author jcarr;	state Exp;
branches;
next	;
commitid	3c1b45c989214567;


desc
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1.1
log
@adding the source directory
@
text
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);
port (

   	-- General 
    clk_i       	: in std_logic;
   	nrst_i       	: in std_logic;
	--  
	adr_i			: in std_logic_vector(5 downto 0);
	cbe_i			: in std_logic_vector(3 downto 0);
	dat_i			: in std_logic_vector(31 downto 0);
	dat_o			: out std_logic_vector(31 downto 0);
	--
	wrcfg_i		   	: in std_logic;
	rdcfg_i 	  	: in std_logic;
	perr_i		  	: in std_logic;
	serr_i		  	: in std_logic;
	tabort_i	  	: in std_logic;
	--
	bar0_o			: out std_logic_vector(31 downto 25);
	perrEN_o		: out std_logic;
	serrEN_o		: out std_logic;
	memEN_o			: out std_logic
		
);   
end pciregs;


architecture rtl of pciregs is


--+-----------------------------------------------------------------------------+
--|									COMPONENTS									|
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--|									CONSTANTS  									|
--+-----------------------------------------------------------------------------+

	constant CLASSCODEr		: std_logic_vector(23 downto 0) := X"028000";   -- Bridge-OtherBridgeDevice
	constant REVISIONIDr	: std_logic_vector(7 downto 0)  := revisionID;	-- PR00=80,PR1=81...
	constant HEADERTYPEr	: std_logic_vector(7 downto 0)  := X"00";		
	constant DEVSELTIMb		: std_logic_vector(1 downto 0)  := b"01";		-- DEVSEL TIMing (bits) medium speed
	constant VENDORIDr		: std_logic_vector(15 downto 0) := vendorID;	
	constant DEVICEIDr		: std_logic_vector(15 downto 0) := deviceID;	
	constant SUBSYSTEMIDr	: std_logic_vector(15 downto 0) := subsystemID;	
	constant SUBSYSTEMVIDr	: std_logic_vector(15 downto 0) := subsystemvID;	
@