head	1.1;
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1.1
date	2007.02.07.08.09.18;	author jcarr;	state Exp;
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commitid	3c1b45c989214567;


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1.1
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@adding the source directory
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@--+-----------------------------------------+
--|  pfs                                    |
--+-----------------------------------------+

library ieee;
use ieee.std_logic_1164.all;

entity pfs is
port (
   clk       	: in std_logic;
   a       	: in std_logic;
   y       	: out std_logic

);   
end pfs;

architecture rtl of pfs is

	signal a_s	: std_logic;
	
begin

	SYNCP: process( clk, a )
	begin
	
        if ( rising_edge(clk) ) then
			a_s <= a;
		end if;
        
	end process SYNCP;

	y <= a and (not a_s);
	
end rtl;

@