head	1.5;
access;
symbols
	spdif_rel_1:1.4
	beta_2:1.4
	rx_beta_1:1.4;
locks; strict;
comment	@# @;


1.5
date	2007.10.11.19.14.43;	author gedra;	state Exp;
branches;
next	1.4;
commitid	350b470e761d4567;

1.4
date	2004.06.26.14.14.47;	author gedra;	state Exp;
branches;
next	1.3;

1.3
date	2004.06.06.15.42.19;	author gedra;	state Exp;
branches;
next	1.2;

1.2
date	2004.06.04.15.55.07;	author gedra;	state Exp;
branches;
next	1.1;

1.1
date	2004.06.03.17.47.17;	author gedra;	state Exp;
branches;
next	;


desc
@@


1.5
log
@Code beautification
@
text
@----------------------------------------------------------------------
----                                                              ----
---- WISHBONE SPDIF IP Core                                       ----
----                                                              ----
---- This file is part of the SPDIF project                       ----
---- http://www.opencores.org/cores/spdif_interface/              ----
----                                                              ----
---- Description                                                  ----
---- Generic control register.                                    ----
----                                                              ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: gen_control_reg.vhd,v $
-- Revision 1.4  2004/06/26 14:14:47  gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.3  2004/06/06 15:42:19  gedra
-- Cleaned up lint warnings.
--
-- Revision 1.2  2004/06/04 15:55:07  gedra
-- Cleaned up lint warnings.
--
-- Revision 1.1  2004/06/03 17:47:17  gedra
-- Generic control register. Used in both recevier and transmitter.
--
--

library ieee;
use ieee.std_logic_1164.all;

entity gen_control_reg is
   generic (DATA_WIDTH      : integer;
            -- note that this vector is (0 to xx), reverse order
            ACTIVE_BIT_MASK : std_logic_vector); 
   port (
      clk       : in  std_logic;        -- clock  
      rst       : in  std_logic;        -- reset
      ctrl_wr   : in  std_logic;        -- control register write  
      ctrl_rd   : in  std_logic;        -- control register read
      ctrl_din  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- write data
      ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- read data
      ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0));  -- control bits
end gen_control_reg;

architecture rtl of gen_control_reg is

   signal ctrl_internal : std_logic_vector(DATA_WIDTH - 1 downto 0);

begin

   ctrl_dout <= ctrl_internal when ctrl_rd = '1' else (others => '0');
   ctrl_bits <= ctrl_internal;

-- control register generation
   CTRLREG : for k in ctrl_din'range generate
      -- active bits can be written to
      ACTIVE : if ACTIVE_BIT_MASK(k) = '1' generate
         CBIT : process (clk, rst)
         begin
            if rst = '1' then
               ctrl_internal(k) <= '0';
            else
               if rising_edge(clk) then
                  if ctrl_wr = '1' then
                     ctrl_internal(k) <= ctrl_din(k);
                  end if;
               end if;
            end if;
         end process CBIT;
      end generate ACTIVE;
      -- inactive bits are always 0
      INACTIVE : if ACTIVE_BIT_MASK(k) = '0' generate
         ctrl_internal(k) <= '0';
      end generate INACTIVE;
   end generate CTRLREG;
   
end rtl;
@


1.4
log
@Converted to numeric_std and fixed a few bugs.
@
text
@d48 3
d63 1
a63 1
use ieee.std_logic_1164.all; 
d65 12
a76 12
entity gen_control_reg is	 
  generic (DATA_WIDTH: integer;
           -- note that this vector is (0 to xx), reverse order
           ACTIVE_BIT_MASK: std_logic_vector); 
  port (                                        
    clk: in std_logic;	 -- clock  
    rst: in std_logic; -- reset
    ctrl_wr: in std_logic; -- control register write	
    ctrl_rd: in std_logic; -- control register read
    ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
    ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
    ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- control bits
d81 1
a81 1
  signal ctrl_internal: std_logic_vector(DATA_WIDTH - 1 downto 0);
d85 3
a87 3
  ctrl_dout <= ctrl_internal when ctrl_rd = '1' else (others => '0');	  
  ctrl_bits <= ctrl_internal;
  
d89 13
a101 11
  CTRLREG: for k in ctrl_din'range generate
    -- active bits can be written to
    ACTIVE: if  ACTIVE_BIT_MASK(k) = '1' generate   
      CBIT: process (clk, rst)
      begin		 
        if rst = '1' then
          ctrl_internal(k) <= '0';
        else
          if rising_edge(clk) then
            if ctrl_wr = '1' then
              ctrl_internal(k) <= ctrl_din(k);
d103 8
a110 10
          end if;	  
        end if;
      end process CBIT;			 	
    end generate ACTIVE;
    -- inactive bits are always 0
    INACTIVE: if ACTIVE_BIT_MASK(k) = '0' generate  
      ctrl_internal(k) <= '0';
    end generate INACTIVE;
  end generate CTRLREG;
  
@


1.3
log
@Cleaned up lint warnings.
@
text
@d48 3
d59 2
a60 3
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all;
@


1.2
log
@Cleaned up lint warnings.
@
text
@d48 3
d62 3
a64 2
           ACTIVE_BIT_MASK: std_logic_vector); -- note that this vector is (0 to xx),
  port (                                       -- reverse order
@


1.1
log
@Generic control register. Used in both recevier and transmitter.
@
text
@d47 4
a50 1
-- $Log$
d58 3
a60 3
  generic (DataWidth: integer;
           ActiveBitsMask: std_logic_vector); -- note that this vector is (0 to xx), reverse order
  port (
d65 3
a67 3
    ctrl_din: in std_logic_vector(DataWidth - 1 downto 0); -- write data
    ctrl_dout: out std_logic_vector(DataWidth - 1 downto 0); -- read data
    ctrl_bits: out std_logic_vector(DataWidth - 1 downto 0)); -- control bits
d72 1
a72 1
  signal ctrl_internal, BitMask: std_logic_vector(DataWidth - 1 downto 0);
d75 1
a75 1
	
d80 3
a82 3
--BitMask <= CONV_STD_LOGIC_VECTOR(ActiveBitsMask, ctrl_din'length);
  CTRLREG: for k in ctrl_din'range generate  
    ACTIVE: if  ActiveBitsMask(k) = '1' generate		 -- active bits can be written to
d95 3
a97 2
    end generate;	 
    INACTIVE: if ActiveBitsMask(k) = '0' generate	-- inactive bits are always 0
d99 2
a100 2
    end generate;
  end generate;
@