head	1.1;
access;
symbols;
locks; strict;
comment	@# @;


1.1
date	2008.08.25.01.31.37;	author sfielding;	state Exp;
branches;
next	;
commitid	226848b20b4c4567;


desc
@@


1.1
log
@spiMaster - First CVS check in
@
text
@[Project]
Current Flow=Generic
VCS=0
version=1
Current Config=compile

[Configurations]
compile=design0

[Library]
design0=.\design0.LIB

[$LibMap$]
design0=.

[Settings]
FLOW_TYPE=HDL
LANGUAGE=VHDL

[file_out:/readWriteSPIWireData.asf]
/\compile\readWriteSPIWireData.v=-1

[file_out:/initSD.asf]
/\compile\initSD.v=-1

[Files]
/readWriteSPIWireData.asf=-1
/initSD.asf=-1
/sendCmd.asf=-1
/readWriteSDBlock.asf=-1
/spiCtrl.asf=-1

[Files.Data]
.\src\readWriteSPIWireData.asf=State Diagram
.\src\initSD.asf=State Diagram
.\src\sendCmd.asf=State Diagram
.\src\readWriteSDBlock.asf=State Diagram
.\src\spiCtrl.asf=State Diagram

[file_out:/sendCmd.asf]
/\compile\sendCmd.v=-1

[file_out:/readWriteSDBlock.asf]
/\compile\readWriteSDBlock.v=-1

[file_out:/spiCtrl.asf]
/\compile\spiCtrl.v=-1

@