head     1.1;
branch   1.1.1;
access   ;
symbols  vlsi:1.1.1.1 marta:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2002.02.09.14.29.58;  author marta;  state Exp;
branches 1.1.1.1;
next     ;

1.1.1.1
date     2002.02.09.14.29.58;  author marta;  state Exp;
branches ;
next     ;


desc
@@



1.1
log
@Initial revision
@
text
@-- VHDL structural description generated from `dec16to288_latch`
--		date : Mon Jul 30 01:37:17 2001


-- Entity Declaration

ENTITY dec16to288_latch IS
  PORT (
  a : in BIT_VECTOR (15 DOWNTO 0);	-- a
  en : in BIT;	-- en
  clr : in BIT;	-- clr
  sel : in BIT_VECTOR (4 DOWNTO 0);	-- sel
  cke : in BIT;	-- cke
  o1 : inout BIT_VECTOR (15 DOWNTO 0);	-- o1
  o2 : inout BIT_VECTOR (15 DOWNTO 0);	-- o2
  o3 : inout BIT_VECTOR (15 DOWNTO 0);	-- o3
  o4 : inout BIT_VECTOR (15 DOWNTO 0);	-- o4
  o5 : inout BIT_VECTOR (15 DOWNTO 0);	-- o5
  o6 : inout BIT_VECTOR (15 DOWNTO 0);	-- o6
  o7 : inout BIT_VECTOR (15 DOWNTO 0);	-- o7
  o8 : inout BIT_VECTOR (15 DOWNTO 0);	-- o8
  o9 : inout BIT_VECTOR (15 DOWNTO 0);	-- o9
  o10 : inout BIT_VECTOR (15 DOWNTO 0);	-- o10
  o11 : inout BIT_VECTOR (15 DOWNTO 0);	-- o11
  o12 : inout BIT_VECTOR (15 DOWNTO 0);	-- o12
  o13 : inout BIT_VECTOR (15 DOWNTO 0);	-- o13
  o14 : inout BIT_VECTOR (15 DOWNTO 0);	-- o14
  o15 : inout BIT_VECTOR (15 DOWNTO 0);	-- o15
  o16 : inout BIT_VECTOR (15 DOWNTO 0);	-- o16
  o17 : inout BIT_VECTOR (15 DOWNTO 0);	-- o17
  o18 : inout BIT_VECTOR (15 DOWNTO 0);	-- o18
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END dec16to288_latch;

-- Architecture Declaration

ARCHITECTURE VST OF dec16to288_latch IS
  COMPONENT dec16to288
    port (
    a : in BIT_VECTOR(15 DOWNTO 0);	-- a
    clr : in BIT;	-- clr
    en : in BIT;	-- en
    sel : in BIT_VECTOR(4 DOWNTO 0);	-- sel
    o1 : out BIT_VECTOR(15 DOWNTO 0);	-- o1
    o2 : out BIT_VECTOR(15 DOWNTO 0);	-- o2
    o3 : out BIT_VECTOR(15 DOWNTO 0);	-- o3
    o4 : out BIT_VECTOR(15 DOWNTO 0);	-- o4
    o5 : out BIT_VECTOR(15 DOWNTO 0);	-- o5
    o6 : out BIT_VECTOR(15 DOWNTO 0);	-- o6
    o7 : out BIT_VECTOR(15 DOWNTO 0);	-- o7
    o8 : out BIT_VECTOR(15 DOWNTO 0);	-- o8
    o9 : out BIT_VECTOR(15 DOWNTO 0);	-- o9
    o10 : out BIT_VECTOR(15 DOWNTO 0);	-- o10
    o11 : out BIT_VECTOR(15 DOWNTO 0);	-- o11
    o12 : out BIT_VECTOR(15 DOWNTO 0);	-- o12
    o13 : out BIT_VECTOR(15 DOWNTO 0);	-- o13
    o14 : out BIT_VECTOR(15 DOWNTO 0);	-- o14
    o15 : out BIT_VECTOR(15 DOWNTO 0);	-- o15
    o16 : out BIT_VECTOR(15 DOWNTO 0);	-- o16
    o17 : out BIT_VECTOR(15 DOWNTO 0);	-- o17
    o18 : out BIT_VECTOR(15 DOWNTO 0);	-- o18
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT latch
    port (
    a : in BIT;	-- a
    en : in BIT;	-- en
    b : inout BIT;	-- b
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  SIGNAL x_0 : BIT;	-- x 0
  SIGNAL x_1 : BIT;	-- x 1
  SIGNAL x_2 : BIT;	-- x 2
  SIGNAL x_3 : BIT;	-- x 3
  SIGNAL x_4 : BIT;	-- x 4
  SIGNAL x_5 : BIT;	-- x 5
  SIGNAL x_6 : BIT;	-- x 6
  SIGNAL x_7 : BIT;	-- x 7
  SIGNAL x_8 : BIT;	-- x 8
  SIGNAL x_9 : BIT;	-- x 9
  SIGNAL x_10 : BIT;	-- x 10
  SIGNAL x_11 : BIT;	-- x 11
  SIGNAL x_12 : BIT;	-- x 12
  SIGNAL x_13 : BIT;	-- x 13
  SIGNAL x_14 : BIT;	-- x 14
  SIGNAL x_15 : BIT;	-- x 15
  SIGNAL x1_0 : BIT;	-- x1 0
  SIGNAL x1_1 : BIT;	-- x1 1
  SIGNAL x1_2 : BIT;	-- x1 2
  SIGNAL x1_3 : BIT;	-- x1 3
  SIGNAL x1_4 : BIT;	-- x1 4
  SIGNAL x1_5 : BIT;	-- x1 5
  SIGNAL x1_6 : BIT;	-- x1 6
  SIGNAL x1_7 : BIT;	-- x1 7
  SIGNAL x1_8 : BIT;	-- x1 8
  SIGNAL x1_9 : BIT;	-- x1 9
  SIGNAL x1_10 : BIT;	-- x1 10
  SIGNAL x1_11 : BIT;	-- x1 11
  SIGNAL x1_12 : BIT;	-- x1 12
  SIGNAL x1_13 : BIT;	-- x1 13
  SIGNAL x1_14 : BIT;	-- x1 14
  SIGNAL x1_15 : BIT;	-- x1 15
  SIGNAL x10_0 : BIT;	-- x10 0
  SIGNAL x10_1 : BIT;	-- x10 1
  SIGNAL x10_2 : BIT;	-- x10 2
  SIGNAL x10_3 : BIT;	-- x10 3
  SIGNAL x10_4 : BIT;	-- x10 4
  SIGNAL x10_5 : BIT;	-- x10 5
  SIGNAL x10_6 : BIT;	-- x10 6
  SIGNAL x10_7 : BIT;	-- x10 7
  SIGNAL x10_8 : BIT;	-- x10 8
  SIGNAL x10_9 : BIT;	-- x10 9
  SIGNAL x10_10 : BIT;	-- x10 10
  SIGNAL x10_11 : BIT;	-- x10 11
  SIGNAL x10_12 : BIT;	-- x10 12
  SIGNAL x10_13 : BIT;	-- x10 13
  SIGNAL x10_14 : BIT;	-- x10 14
  SIGNAL x10_15 : BIT;	-- x10 15
  SIGNAL x11_0 : BIT;	-- x11 0
  SIGNAL x11_1 : BIT;	-- x11 1
  SIGNAL x11_2 : BIT;	-- x11 2
  SIGNAL x11_3 : BIT;	-- x11 3
  SIGNAL x11_4 : BIT;	-- x11 4
  SIGNAL x11_5 : BIT;	-- x11 5
  SIGNAL x11_6 : BIT;	-- x11 6
  SIGNAL x11_7 : BIT;	-- x11 7
  SIGNAL x11_8 : BIT;	-- x11 8
  SIGNAL x11_9 : BIT;	-- x11 9
  SIGNAL x11_10 : BIT;	-- x11 10
  SIGNAL x11_11 : BIT;	-- x11 11
  SIGNAL x11_12 : BIT;	-- x11 12
  SIGNAL x11_13 : BIT;	-- x11 13
  SIGNAL x11_14 : BIT;	-- x11 14
  SIGNAL x11_15 : BIT;	-- x11 15
  SIGNAL x12_0 : BIT;	-- x12 0
  SIGNAL x12_1 : BIT;	-- x12 1
  SIGNAL x12_2 : BIT;	-- x12 2
  SIGNAL x12_3 : BIT;	-- x12 3
  SIGNAL x12_4 : BIT;	-- x12 4
  SIGNAL x12_5 : BIT;	-- x12 5
  SIGNAL x12_6 : BIT;	-- x12 6
  SIGNAL x12_7 : BIT;	-- x12 7
  SIGNAL x12_8 : BIT;	-- x12 8
  SIGNAL x12_9 : BIT;	-- x12 9
  SIGNAL x12_10 : BIT;	-- x12 10
  SIGNAL x12_11 : BIT;	-- x12 11
  SIGNAL x12_12 : BIT;	-- x12 12
  SIGNAL x12_13 : BIT;	-- x12 13
  SIGNAL x12_14 : BIT;	-- x12 14
  SIGNAL x12_15 : BIT;	-- x12 15
  SIGNAL x13_0 : BIT;	-- x13 0
  SIGNAL x13_1 : BIT;	-- x13 1
  SIGNAL x13_2 : BIT;	-- x13 2
  SIGNAL x13_3 : BIT;	-- x13 3
  SIGNAL x13_4 : BIT;	-- x13 4
  SIGNAL x13_5 : BIT;	-- x13 5
  SIGNAL x13_6 : BIT;	-- x13 6
  SIGNAL x13_7 : BIT;	-- x13 7
  SIGNAL x13_8 : BIT;	-- x13 8
  SIGNAL x13_9 : BIT;	-- x13 9
  SIGNAL x13_10 : BIT;	-- x13 10
  SIGNAL x13_11 : BIT;	-- x13 11
  SIGNAL x13_12 : BIT;	-- x13 12
  SIGNAL x13_13 : BIT;	-- x13 13
  SIGNAL x13_14 : BIT;	-- x13 14
  SIGNAL x13_15 : BIT;	-- x13 15
  SIGNAL x14_0 : BIT;	-- x14 0
  SIGNAL x14_1 : BIT;	-- x14 1
  SIGNAL x14_2 : BIT;	-- x14 2
  SIGNAL x14_3 : BIT;	-- x14 3
  SIGNAL x14_4 : BIT;	-- x14 4
  SIGNAL x14_5 : BIT;	-- x14 5
  SIGNAL x14_6 : BIT;	-- x14 6
  SIGNAL x14_7 : BIT;	-- x14 7
  SIGNAL x14_8 : BIT;	-- x14 8
  SIGNAL x14_9 : BIT;	-- x14 9
  SIGNAL x14_10 : BIT;	-- x14 10
  SIGNAL x14_11 : BIT;	-- x14 11
  SIGNAL x14_12 : BIT;	-- x14 12
  SIGNAL x14_13 : BIT;	-- x14 13
  SIGNAL x14_14 : BIT;	-- x14 14
  SIGNAL x14_15 : BIT;	-- x14 15
  SIGNAL x15_0 : BIT;	-- x15 0
  SIGNAL x15_1 : BIT;	-- x15 1
  SIGNAL x15_2 : BIT;	-- x15 2
  SIGNAL x15_3 : BIT;	-- x15 3
  SIGNAL x15_4 : BIT;	-- x15 4
  SIGNAL x15_5 : BIT;	-- x15 5
  SIGNAL x15_6 : BIT;	-- x15 6
  SIGNAL x15_7 : BIT;	-- x15 7
  SIGNAL x15_8 : BIT;	-- x15 8
  SIGNAL x15_9 : BIT;	-- x15 9
  SIGNAL x15_10 : BIT;	-- x15 10
  SIGNAL x15_11 : BIT;	-- x15 11
  SIGNAL x15_12 : BIT;	-- x15 12
  SIGNAL x15_13 : BIT;	-- x15 13
  SIGNAL x15_14 : BIT;	-- x15 14
  SIGNAL x15_15 : BIT;	-- x15 15
  SIGNAL x16_0 : BIT;	-- x16 0
  SIGNAL x16_1 : BIT;	-- x16 1
  SIGNAL x16_2 : BIT;	-- x16 2
  SIGNAL x16_3 : BIT;	-- x16 3
  SIGNAL x16_4 : BIT;	-- x16 4
  SIGNAL x16_5 : BIT;	-- x16 5
  SIGNAL x16_6 : BIT;	-- x16 6
  SIGNAL x16_7 : BIT;	-- x16 7
  SIGNAL x16_8 : BIT;	-- x16 8
  SIGNAL x16_9 : BIT;	-- x16 9
  SIGNAL x16_10 : BIT;	-- x16 10
  SIGNAL x16_11 : BIT;	-- x16 11
  SIGNAL x16_12 : BIT;	-- x16 12
  SIGNAL x16_13 : BIT;	-- x16 13
  SIGNAL x16_14 : BIT;	-- x16 14
  SIGNAL x16_15 : BIT;	-- x16 15
  SIGNAL x17_0 : BIT;	-- x17 0
  SIGNAL x17_1 : BIT;	-- x17 1
  SIGNAL x17_2 : BIT;	-- x17 2
  SIGNAL x17_3 : BIT;	-- x17 3
  SIGNAL x17_4 : BIT;	-- x17 4
  SIGNAL x17_5 : BIT;	-- x17 5
  SIGNAL x17_6 : BIT;	-- x17 6
  SIGNAL x17_7 : BIT;	-- x17 7
  SIGNAL x17_8 : BIT;	-- x17 8
  SIGNAL x17_9 : BIT;	-- x17 9
  SIGNAL x17_10 : BIT;	-- x17 10
  SIGNAL x17_11 : BIT;	-- x17 11
  SIGNAL x17_12 : BIT;	-- x17 12
  SIGNAL x17_13 : BIT;	-- x17 13
  SIGNAL x17_14 : BIT;	-- x17 14
  SIGNAL x17_15 : BIT;	-- x17 15
  SIGNAL x18_0 : BIT;	-- x18 0
  SIGNAL x18_1 : BIT;	-- x18 1
  SIGNAL x18_2 : BIT;	-- x18 2
  SIGNAL x18_3 : BIT;	-- x18 3
  SIGNAL x18_4 : BIT;	-- x18 4
  SIGNAL x18_5 : BIT;	-- x18 5
  SIGNAL x18_6 : BIT;	-- x18 6
  SIGNAL x18_7 : BIT;	-- x18 7
  SIGNAL x18_8 : BIT;	-- x18 8
  SIGNAL x18_9 : BIT;	-- x18 9
  SIGNAL x18_10 : BIT;	-- x18 10
  SIGNAL x18_11 : BIT;	-- x18 11
  SIGNAL x18_12 : BIT;	-- x18 12
  SIGNAL x18_13 : BIT;	-- x18 13
  SIGNAL x18_14 : BIT;	-- x18 14
  SIGNAL x18_15 : BIT;	-- x18 15
  SIGNAL x2_0 : BIT;	-- x2 0
  SIGNAL x2_1 : BIT;	-- x2 1
  SIGNAL x2_2 : BIT;	-- x2 2
  SIGNAL x2_3 : BIT;	-- x2 3
  SIGNAL x2_4 : BIT;	-- x2 4
  SIGNAL x2_5 : BIT;	-- x2 5
  SIGNAL x2_6 : BIT;	-- x2 6
  SIGNAL x2_7 : BIT;	-- x2 7
  SIGNAL x2_8 : BIT;	-- x2 8
  SIGNAL x2_9 : BIT;	-- x2 9
  SIGNAL x2_10 : BIT;	-- x2 10
  SIGNAL x2_11 : BIT;	-- x2 11
  SIGNAL x2_12 : BIT;	-- x2 12
  SIGNAL x2_13 : BIT;	-- x2 13
  SIGNAL x2_14 : BIT;	-- x2 14
  SIGNAL x2_15 : BIT;	-- x2 15
  SIGNAL x3_0 : BIT;	-- x3 0
  SIGNAL x3_1 : BIT;	-- x3 1
  SIGNAL x3_2 : BIT;	-- x3 2
  SIGNAL x3_3 : BIT;	-- x3 3
  SIGNAL x3_4 : BIT;	-- x3 4
  SIGNAL x3_5 : BIT;	-- x3 5
  SIGNAL x3_6 : BIT;	-- x3 6
  SIGNAL x3_7 : BIT;	-- x3 7
  SIGNAL x3_8 : BIT;	-- x3 8
  SIGNAL x3_9 : BIT;	-- x3 9
  SIGNAL x3_10 : BIT;	-- x3 10
  SIGNAL x3_11 : BIT;	-- x3 11
  SIGNAL x3_12 : BIT;	-- x3 12
  SIGNAL x3_13 : BIT;	-- x3 13
  SIGNAL x3_14 : BIT;	-- x3 14
  SIGNAL x3_15 : BIT;	-- x3 15
  SIGNAL x4_0 : BIT;	-- x4 0
  SIGNAL x4_1 : BIT;	-- x4 1
  SIGNAL x4_2 : BIT;	-- x4 2
  SIGNAL x4_3 : BIT;	-- x4 3
  SIGNAL x4_4 : BIT;	-- x4 4
  SIGNAL x4_5 : BIT;	-- x4 5
  SIGNAL x4_6 : BIT;	-- x4 6
  SIGNAL x4_7 : BIT;	-- x4 7
  SIGNAL x4_8 : BIT;	-- x4 8
  SIGNAL x4_9 : BIT;	-- x4 9
  SIGNAL x4_10 : BIT;	-- x4 10
  SIGNAL x4_11 : BIT;	-- x4 11
  SIGNAL x4_12 : BIT;	-- x4 12
  SIGNAL x4_13 : BIT;	-- x4 13
  SIGNAL x4_14 : BIT;	-- x4 14
  SIGNAL x4_15 : BIT;	-- x4 15
  SIGNAL x5_0 : BIT;	-- x5 0
  SIGNAL x5_1 : BIT;	-- x5 1
  SIGNAL x5_2 : BIT;	-- x5 2
  SIGNAL x5_3 : BIT;	-- x5 3
  SIGNAL x5_4 : BIT;	-- x5 4
  SIGNAL x5_5 : BIT;	-- x5 5
  SIGNAL x5_6 : BIT;	-- x5 6
  SIGNAL x5_7 : BIT;	-- x5 7
  SIGNAL x5_8 : BIT;	-- x5 8
  SIGNAL x5_9 : BIT;	-- x5 9
  SIGNAL x5_10 : BIT;	-- x5 10
  SIGNAL x5_11 : BIT;	-- x5 11
  SIGNAL x5_12 : BIT;	-- x5 12
  SIGNAL x5_13 : BIT;	-- x5 13
  SIGNAL x5_14 : BIT;	-- x5 14
  SIGNAL x5_15 : BIT;	-- x5 15
  SIGNAL x6_0 : BIT;	-- x6 0
  SIGNAL x6_1 : BIT;	-- x6 1
  SIGNAL x6_2 : BIT;	-- x6 2
  SIGNAL x6_3 : BIT;	-- x6 3
  SIGNAL x6_4 : BIT;	-- x6 4
  SIGNAL x6_5 : BIT;	-- x6 5
  SIGNAL x6_6 : BIT;	-- x6 6
  SIGNAL x6_7 : BIT;	-- x6 7
  SIGNAL x6_8 : BIT;	-- x6 8
  SIGNAL x6_9 : BIT;	-- x6 9
  SIGNAL x6_10 : BIT;	-- x6 10
  SIGNAL x6_11 : BIT;	-- x6 11
  SIGNAL x6_12 : BIT;	-- x6 12
  SIGNAL x6_13 : BIT;	-- x6 13
  SIGNAL x6_14 : BIT;	-- x6 14
  SIGNAL x6_15 : BIT;	-- x6 15
  SIGNAL x7_0 : BIT;	-- x7 0
  SIGNAL x7_1 : BIT;	-- x7 1
  SIGNAL x7_2 : BIT;	-- x7 2
  SIGNAL x7_3 : BIT;	-- x7 3
  SIGNAL x7_4 : BIT;	-- x7 4
  SIGNAL x7_5 : BIT;	-- x7 5
  SIGNAL x7_6 : BIT;	-- x7 6
  SIGNAL x7_7 : BIT;	-- x7 7
  SIGNAL x7_8 : BIT;	-- x7 8
  SIGNAL x7_9 : BIT;	-- x7 9
  SIGNAL x7_10 : BIT;	-- x7 10
  SIGNAL x7_11 : BIT;	-- x7 11
  SIGNAL x7_12 : BIT;	-- x7 12
  SIGNAL x7_13 : BIT;	-- x7 13
  SIGNAL x7_14 : BIT;	-- x7 14
  SIGNAL x7_15 : BIT;	-- x7 15
  SIGNAL x8_0 : BIT;	-- x8 0
  SIGNAL x8_1 : BIT;	-- x8 1
  SIGNAL x8_2 : BIT;	-- x8 2
  SIGNAL x8_3 : BIT;	-- x8 3
  SIGNAL x8_4 : BIT;	-- x8 4
  SIGNAL x8_5 : BIT;	-- x8 5
  SIGNAL x8_6 : BIT;	-- x8 6
  SIGNAL x8_7 : BIT;	-- x8 7
  SIGNAL x8_8 : BIT;	-- x8 8
  SIGNAL x8_9 : BIT;	-- x8 9
  SIGNAL x8_10 : BIT;	-- x8 10
  SIGNAL x8_11 : BIT;	-- x8 11
  SIGNAL x8_12 : BIT;	-- x8 12
  SIGNAL x8_13 : BIT;	-- x8 13
  SIGNAL x8_14 : BIT;	-- x8 14
  SIGNAL x8_15 : BIT;	-- x8 15
  SIGNAL x9_0 : BIT;	-- x9 0
  SIGNAL x9_1 : BIT;	-- x9 1
  SIGNAL x9_2 : BIT;	-- x9 2
  SIGNAL x9_3 : BIT;	-- x9 3
  SIGNAL x9_4 : BIT;	-- x9 4
  SIGNAL x9_5 : BIT;	-- x9 5
  SIGNAL x9_6 : BIT;	-- x9 6
  SIGNAL x9_7 : BIT;	-- x9 7
  SIGNAL x9_8 : BIT;	-- x9 8
  SIGNAL x9_9 : BIT;	-- x9 9
  SIGNAL x9_10 : BIT;	-- x9 10
  SIGNAL x9_11 : BIT;	-- x9 11
  SIGNAL x9_12 : BIT;	-- x9 12
  SIGNAL x9_13 : BIT;	-- x9 13
  SIGNAL x9_14 : BIT;	-- x9 14
  SIGNAL x9_15 : BIT;	-- x9 15

BEGIN

  dec1 : dec16to288
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o18 => x18_15& x18_14& x18_13& x18_12& x18_11& x18_10& x18_9& x18_8& x18_7& x18_6& x18_5& x18_4& x18_3& x18_2& x18_1& x18_0,
    o17 => x17_15& x17_14& x17_13& x17_12& x17_11& x17_10& x17_9& x17_8& x17_7& x17_6& x17_5& x17_4& x17_3& x17_2& x17_1& x17_0,
    o16 => x16_15& x16_14& x16_13& x16_12& x16_11& x16_10& x16_9& x16_8& x16_7& x16_6& x16_5& x16_4& x16_3& x16_2& x16_1& x16_0,
    o15 => x15_15& x15_14& x15_13& x15_12& x15_11& x15_10& x15_9& x15_8& x15_7& x15_6& x15_5& x15_4& x15_3& x15_2& x15_1& x15_0,
    o14 => x14_15& x14_14& x14_13& x14_12& x14_11& x14_10& x14_9& x14_8& x14_7& x14_6& x14_5& x14_4& x14_3& x14_2& x14_1& x14_0,
    o13 => x13_15& x13_14& x13_13& x13_12& x13_11& x13_10& x13_9& x13_8& x13_7& x13_6& x13_5& x13_4& x13_3& x13_2& x13_1& x13_0,
    o12 => x12_15& x12_14& x12_13& x12_12& x12_11& x12_10& x12_9& x12_8& x12_7& x12_6& x12_5& x12_4& x12_3& x12_2& x12_1& x12_0,
    o11 => x11_15& x11_14& x11_13& x11_12& x11_11& x11_10& x11_9& x11_8& x11_7& x11_6& x11_5& x11_4& x11_3& x11_2& x11_1& x11_0,
    o10 => x10_15& x10_14& x10_13& x10_12& x10_11& x10_10& x10_9& x10_8& x10_7& x10_6& x10_5& x10_4& x10_3& x10_2& x10_1& x10_0,
    o9 => x9_15& x9_14& x9_13& x9_12& x9_11& x9_10& x9_9& x9_8& x9_7& x9_6& x9_5& x9_4& x9_3& x9_2& x9_1& x9_0,
    o8 => x8_15& x8_14& x8_13& x8_12& x8_11& x8_10& x8_9& x8_8& x8_7& x8_6& x8_5& x8_4& x8_3& x8_2& x8_1& x8_0,
    o7 => x7_15& x7_14& x7_13& x7_12& x7_11& x7_10& x7_9& x7_8& x7_7& x7_6& x7_5& x7_4& x7_3& x7_2& x7_1& x7_0,
    o6 => x6_15& x6_14& x6_13& x6_12& x6_11& x6_10& x6_9& x6_8& x6_7& x6_6& x6_5& x6_4& x6_3& x6_2& x6_1& x6_0,
    o5 => x5_15& x5_14& x5_13& x5_12& x5_11& x5_10& x5_9& x5_8& x5_7& x5_6& x5_5& x5_4& x5_3& x5_2& x5_1& x5_0,
    o4 => x_15& x_14& x_13& x_12& x_11& x_10& x_9& x_8& x_7& x_6& x_5& x_4& x_3& x_2& x_1& x_0,
    o3 => x3_15& x3_14& x3_13& x3_12& x3_11& x3_10& x3_9& x3_8& x3_7& x3_6& x3_5& x3_4& x3_3& x3_2& x3_1& x3_0,
    o2 => x2_15& x2_14& x2_13& x2_12& x2_11& x2_10& x2_9& x2_8& x2_7& x2_6& x2_5& x2_4& x2_3& x2_2& x2_1& x2_0,
    o1 => x1_15& x1_14& x1_13& x1_12& x1_11& x1_10& x1_9& x1_8& x1_7& x1_6& x1_5& x1_4& x1_3& x1_2& x1_1& x1_0,
    sel => sel(4)& sel(3)& sel(2)& sel(1)& sel(0),
    en => clr,
    clr => en,
    a => a(15)& a(14)& a(13)& a(12)& a(11)& a(10)& a(9)& a(8)& a(7)& a(6)& a(5)& a(4)& a(3)& a(2)& a(1)& a(0));
  latch0 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(0),
    en => cke,
    a => x1_0);
  latch16 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(0),
    en => cke,
    a => x2_0);
  latch32 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(0),
    en => cke,
    a => x3_0);
  latch48 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(0),
    en => cke,
    a => x4_0);
  latch64 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(0),
    en => cke,
    a => x5_0);
  latch80 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(0),
    en => cke,
    a => x6_0);
  latch96 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(0),
    en => cke,
    a => x7_0);
  latch112 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(0),
    en => cke,
    a => x8_0);
  latch128 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(0),
    en => cke,
    a => x9_0);
  latch144 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(0),
    en => cke,
    a => x10_0);
  latch160 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(0),
    en => cke,
    a => x11_0);
  latch176 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(0),
    en => cke,
    a => x12_0);
  latch192 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(0),
    en => cke,
    a => x13_0);
  latch208 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(0),
    en => cke,
    a => x14_0);
  latch224 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(0),
    en => cke,
    a => x15_0);
  latch240 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(0),
    en => cke,
    a => x16_0);
  latch256 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(0),
    en => cke,
    a => x17_0);
  latch272 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(0),
    en => cke,
    a => x18_0);
  latch1 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(1),
    en => cke,
    a => x1_1);
  latch17 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(1),
    en => cke,
    a => x2_1);
  latch33 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(1),
    en => cke,
    a => x3_1);
  latch49 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(1),
    en => cke,
    a => x4_1);
  latch65 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(1),
    en => cke,
    a => x5_1);
  latch81 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(1),
    en => cke,
    a => x6_1);
  latch97 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(1),
    en => cke,
    a => x7_1);
  latch113 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(1),
    en => cke,
    a => x8_1);
  latch129 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(1),
    en => cke,
    a => x9_1);
  latch145 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(1),
    en => cke,
    a => x10_1);
  latch161 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(1),
    en => cke,
    a => x11_1);
  latch177 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(1),
    en => cke,
    a => x12_1);
  latch193 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(1),
    en => cke,
    a => x13_1);
  latch209 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(1),
    en => cke,
    a => x14_1);
  latch225 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(1),
    en => cke,
    a => x15_1);
  latch241 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(1),
    en => cke,
    a => x16_1);
  latch257 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(1),
    en => cke,
    a => x17_1);
  latch273 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(1),
    en => cke,
    a => x18_1);
  latch2 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(2),
    en => cke,
    a => x1_2);
  latch18 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(2),
    en => cke,
    a => x2_2);
  latch34 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(2),
    en => cke,
    a => x3_2);
  latch50 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(2),
    en => cke,
    a => x4_2);
  latch66 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(2),
    en => cke,
    a => x5_2);
  latch82 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(2),
    en => cke,
    a => x6_2);
  latch98 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(2),
    en => cke,
    a => x7_2);
  latch114 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(2),
    en => cke,
    a => x8_2);
  latch130 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(2),
    en => cke,
    a => x9_2);
  latch146 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(2),
    en => cke,
    a => x10_2);
  latch162 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(2),
    en => cke,
    a => x11_2);
  latch178 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(2),
    en => cke,
    a => x12_2);
  latch194 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(2),
    en => cke,
    a => x13_2);
  latch210 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(2),
    en => cke,
    a => x14_2);
  latch226 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(2),
    en => cke,
    a => x15_2);
  latch242 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(2),
    en => cke,
    a => x16_2);
  latch258 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(2),
    en => cke,
    a => x17_2);
  latch274 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(2),
    en => cke,
    a => x18_2);
  latch3 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(3),
    en => cke,
    a => x1_3);
  latch19 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(3),
    en => cke,
    a => x2_3);
  latch35 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(3),
    en => cke,
    a => x3_3);
  latch51 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(3),
    en => cke,
    a => x4_3);
  latch67 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(3),
    en => cke,
    a => x5_3);
  latch83 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(3),
    en => cke,
    a => x6_3);
  latch99 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(3),
    en => cke,
    a => x7_3);
  latch115 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(3),
    en => cke,
    a => x8_3);
  latch131 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(3),
    en => cke,
    a => x9_3);
  latch147 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(3),
    en => cke,
    a => x10_3);
  latch163 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(3),
    en => cke,
    a => x11_3);
  latch179 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(3),
    en => cke,
    a => x12_3);
  latch195 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(3),
    en => cke,
    a => x13_3);
  latch211 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(3),
    en => cke,
    a => x14_3);
  latch227 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(3),
    en => cke,
    a => x15_3);
  latch243 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(3),
    en => cke,
    a => x16_3);
  latch259 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(3),
    en => cke,
    a => x17_3);
  latch275 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(3),
    en => cke,
    a => x18_3);
  latch4 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(4),
    en => cke,
    a => x1_4);
  latch20 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(4),
    en => cke,
    a => x2_4);
  latch36 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(4),
    en => cke,
    a => x3_4);
  latch52 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(4),
    en => cke,
    a => x4_4);
  latch68 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(4),
    en => cke,
    a => x5_4);
  latch84 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(4),
    en => cke,
    a => x6_4);
  latch100 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(4),
    en => cke,
    a => x7_4);
  latch116 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(4),
    en => cke,
    a => x8_4);
  latch132 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(4),
    en => cke,
    a => x9_4);
  latch148 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(4),
    en => cke,
    a => x10_4);
  latch164 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(4),
    en => cke,
    a => x11_4);
  latch180 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(4),
    en => cke,
    a => x12_4);
  latch196 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(4),
    en => cke,
    a => x13_4);
  latch212 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(4),
    en => cke,
    a => x14_4);
  latch228 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(4),
    en => cke,
    a => x15_4);
  latch244 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(4),
    en => cke,
    a => x16_4);
  latch260 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(4),
    en => cke,
    a => x17_4);
  latch276 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(4),
    en => cke,
    a => x18_4);
  latch5 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(5),
    en => cke,
    a => x1_5);
  latch21 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(5),
    en => cke,
    a => x2_5);
  latch37 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(5),
    en => cke,
    a => x3_5);
  latch53 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(5),
    en => cke,
    a => x4_5);
  latch69 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(5),
    en => cke,
    a => x5_5);
  latch85 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(5),
    en => cke,
    a => x6_5);
  latch101 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(5),
    en => cke,
    a => x7_5);
  latch117 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(5),
    en => cke,
    a => x8_5);
  latch133 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(5),
    en => cke,
    a => x9_5);
  latch149 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(5),
    en => cke,
    a => x10_5);
  latch165 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(5),
    en => cke,
    a => x11_5);
  latch181 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(5),
    en => cke,
    a => x12_5);
  latch197 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(5),
    en => cke,
    a => x13_5);
  latch213 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(5),
    en => cke,
    a => x14_5);
  latch229 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(5),
    en => cke,
    a => x15_5);
  latch245 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(5),
    en => cke,
    a => x16_5);
  latch261 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(5),
    en => cke,
    a => x17_5);
  latch277 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(5),
    en => cke,
    a => x18_5);
  latch6 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(6),
    en => cke,
    a => x1_6);
  latch22 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(6),
    en => cke,
    a => x2_6);
  latch38 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(6),
    en => cke,
    a => x3_6);
  latch54 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(6),
    en => cke,
    a => x4_6);
  latch70 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(6),
    en => cke,
    a => x5_6);
  latch86 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(6),
    en => cke,
    a => x6_6);
  latch102 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(6),
    en => cke,
    a => x7_6);
  latch118 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(6),
    en => cke,
    a => x8_6);
  latch134 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(6),
    en => cke,
    a => x9_6);
  latch150 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(6),
    en => cke,
    a => x10_6);
  latch166 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(6),
    en => cke,
    a => x11_6);
  latch182 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(6),
    en => cke,
    a => x12_6);
  latch198 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(6),
    en => cke,
    a => x13_6);
  latch214 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(6),
    en => cke,
    a => x14_6);
  latch230 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(6),
    en => cke,
    a => x15_6);
  latch246 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(6),
    en => cke,
    a => x16_6);
  latch262 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(6),
    en => cke,
    a => x17_6);
  latch278 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(6),
    en => cke,
    a => x18_6);
  latch7 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(7),
    en => cke,
    a => x1_7);
  latch23 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(7),
    en => cke,
    a => x2_7);
  latch39 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(7),
    en => cke,
    a => x3_7);
  latch55 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(7),
    en => cke,
    a => x4_7);
  latch71 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(7),
    en => cke,
    a => x5_7);
  latch87 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(7),
    en => cke,
    a => x6_7);
  latch103 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(7),
    en => cke,
    a => x7_7);
  latch119 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(7),
    en => cke,
    a => x8_7);
  latch135 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(7),
    en => cke,
    a => x9_7);
  latch151 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(7),
    en => cke,
    a => x10_7);
  latch167 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(7),
    en => cke,
    a => x11_7);
  latch183 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(7),
    en => cke,
    a => x12_7);
  latch199 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(7),
    en => cke,
    a => x13_7);
  latch215 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(7),
    en => cke,
    a => x14_7);
  latch231 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(7),
    en => cke,
    a => x15_7);
  latch247 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(7),
    en => cke,
    a => x16_7);
  latch263 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(7),
    en => cke,
    a => x17_7);
  latch279 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(7),
    en => cke,
    a => x18_7);
  latch8 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(8),
    en => cke,
    a => x1_8);
  latch24 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(8),
    en => cke,
    a => x2_8);
  latch40 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(8),
    en => cke,
    a => x3_8);
  latch56 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(8),
    en => cke,
    a => x4_8);
  latch72 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(8),
    en => cke,
    a => x5_8);
  latch88 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(8),
    en => cke,
    a => x6_8);
  latch104 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(8),
    en => cke,
    a => x7_8);
  latch120 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(8),
    en => cke,
    a => x8_8);
  latch136 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(8),
    en => cke,
    a => x9_8);
  latch152 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(8),
    en => cke,
    a => x10_8);
  latch168 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(8),
    en => cke,
    a => x11_8);
  latch184 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(8),
    en => cke,
    a => x12_8);
  latch200 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(8),
    en => cke,
    a => x13_8);
  latch216 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(8),
    en => cke,
    a => x14_8);
  latch232 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(8),
    en => cke,
    a => x15_8);
  latch248 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(8),
    en => cke,
    a => x16_8);
  latch264 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(8),
    en => cke,
    a => x17_8);
  latch280 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(8),
    en => cke,
    a => x18_8);
  latch9 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(9),
    en => cke,
    a => x1_9);
  latch25 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(9),
    en => cke,
    a => x2_9);
  latch41 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(9),
    en => cke,
    a => x3_9);
  latch57 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(9),
    en => cke,
    a => x4_9);
  latch73 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(9),
    en => cke,
    a => x5_9);
  latch89 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(9),
    en => cke,
    a => x6_9);
  latch105 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(9),
    en => cke,
    a => x7_9);
  latch121 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(9),
    en => cke,
    a => x8_9);
  latch137 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(9),
    en => cke,
    a => x9_9);
  latch153 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(9),
    en => cke,
    a => x10_9);
  latch169 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(9),
    en => cke,
    a => x11_9);
  latch185 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(9),
    en => cke,
    a => x12_9);
  latch201 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(9),
    en => cke,
    a => x13_9);
  latch217 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(9),
    en => cke,
    a => x14_9);
  latch233 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(9),
    en => cke,
    a => x15_9);
  latch249 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(9),
    en => cke,
    a => x16_9);
  latch265 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(9),
    en => cke,
    a => x17_9);
  latch281 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(9),
    en => cke,
    a => x18_9);
  latch10 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(10),
    en => cke,
    a => x1_10);
  latch26 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(10),
    en => cke,
    a => x2_10);
  latch42 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(10),
    en => cke,
    a => x3_10);
  latch58 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(10),
    en => cke,
    a => x4_10);
  latch74 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(10),
    en => cke,
    a => x5_10);
  latch90 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(10),
    en => cke,
    a => x6_10);
  latch106 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(10),
    en => cke,
    a => x7_10);
  latch122 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(10),
    en => cke,
    a => x8_10);
  latch138 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(10),
    en => cke,
    a => x9_10);
  latch154 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(10),
    en => cke,
    a => x10_10);
  latch170 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(10),
    en => cke,
    a => x11_10);
  latch186 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(10),
    en => cke,
    a => x12_10);
  latch202 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(10),
    en => cke,
    a => x13_10);
  latch218 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(10),
    en => cke,
    a => x14_10);
  latch234 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(10),
    en => cke,
    a => x15_10);
  latch250 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(10),
    en => cke,
    a => x16_10);
  latch266 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(10),
    en => cke,
    a => x17_10);
  latch282 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(10),
    en => cke,
    a => x18_10);
  latch11 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(11),
    en => cke,
    a => x1_11);
  latch27 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(11),
    en => cke,
    a => x2_11);
  latch43 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(11),
    en => cke,
    a => x3_11);
  latch59 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(11),
    en => cke,
    a => x4_11);
  latch75 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(11),
    en => cke,
    a => x5_11);
  latch91 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(11),
    en => cke,
    a => x6_11);
  latch107 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(11),
    en => cke,
    a => x7_11);
  latch123 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(11),
    en => cke,
    a => x8_11);
  latch139 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(11),
    en => cke,
    a => x9_11);
  latch155 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(11),
    en => cke,
    a => x10_11);
  latch171 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(11),
    en => cke,
    a => x11_11);
  latch187 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(11),
    en => cke,
    a => x12_11);
  latch203 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(11),
    en => cke,
    a => x13_11);
  latch219 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(11),
    en => cke,
    a => x14_11);
  latch235 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(11),
    en => cke,
    a => x15_11);
  latch251 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(11),
    en => cke,
    a => x16_11);
  latch267 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(11),
    en => cke,
    a => x17_11);
  latch283 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(11),
    en => cke,
    a => x18_11);
  latch12 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(12),
    en => cke,
    a => x1_12);
  latch28 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(12),
    en => cke,
    a => x2_12);
  latch44 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(12),
    en => cke,
    a => x3_12);
  latch60 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(12),
    en => cke,
    a => x4_12);
  latch76 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(12),
    en => cke,
    a => x5_12);
  latch92 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(12),
    en => cke,
    a => x6_12);
  latch108 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(12),
    en => cke,
    a => x7_12);
  latch124 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(12),
    en => cke,
    a => x8_12);
  latch140 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(12),
    en => cke,
    a => x9_12);
  latch156 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(12),
    en => cke,
    a => x10_12);
  latch172 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(12),
    en => cke,
    a => x11_12);
  latch188 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(12),
    en => cke,
    a => x12_12);
  latch204 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(12),
    en => cke,
    a => x13_12);
  latch220 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(12),
    en => cke,
    a => x14_12);
  latch236 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(12),
    en => cke,
    a => x15_12);
  latch252 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(12),
    en => cke,
    a => x16_12);
  latch268 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(12),
    en => cke,
    a => x17_12);
  latch284 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(12),
    en => cke,
    a => x18_12);
  latch13 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(13),
    en => cke,
    a => x1_13);
  latch29 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(13),
    en => cke,
    a => x2_13);
  latch45 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(13),
    en => cke,
    a => x3_13);
  latch61 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(13),
    en => cke,
    a => x4_13);
  latch77 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(13),
    en => cke,
    a => x5_13);
  latch93 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(13),
    en => cke,
    a => x6_13);
  latch109 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(13),
    en => cke,
    a => x7_13);
  latch125 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(13),
    en => cke,
    a => x8_13);
  latch141 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(13),
    en => cke,
    a => x9_13);
  latch157 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(13),
    en => cke,
    a => x10_13);
  latch173 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(13),
    en => cke,
    a => x11_13);
  latch189 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(13),
    en => cke,
    a => x12_13);
  latch205 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(13),
    en => cke,
    a => x13_13);
  latch221 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(13),
    en => cke,
    a => x14_13);
  latch237 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(13),
    en => cke,
    a => x15_13);
  latch253 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(13),
    en => cke,
    a => x16_13);
  latch269 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(13),
    en => cke,
    a => x17_13);
  latch285 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(13),
    en => cke,
    a => x18_13);
  latch14 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(14),
    en => cke,
    a => x1_14);
  latch30 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(14),
    en => cke,
    a => x2_14);
  latch46 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(14),
    en => cke,
    a => x3_14);
  latch62 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(14),
    en => cke,
    a => x4_14);
  latch78 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(14),
    en => cke,
    a => x5_14);
  latch94 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(14),
    en => cke,
    a => x6_14);
  latch110 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(14),
    en => cke,
    a => x7_14);
  latch126 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(14),
    en => cke,
    a => x8_14);
  latch142 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(14),
    en => cke,
    a => x9_14);
  latch158 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(14),
    en => cke,
    a => x10_14);
  latch174 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(14),
    en => cke,
    a => x11_14);
  latch190 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(14),
    en => cke,
    a => x12_14);
  latch206 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(14),
    en => cke,
    a => x13_14);
  latch222 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(14),
    en => cke,
    a => x14_14);
  latch238 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(14),
    en => cke,
    a => x15_14);
  latch254 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(14),
    en => cke,
    a => x16_14);
  latch270 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(14),
    en => cke,
    a => x17_14);
  latch286 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(14),
    en => cke,
    a => x18_14);
  latch15 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(15),
    en => cke,
    a => x1_15);
  latch31 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(15),
    en => cke,
    a => x2_15);
  latch47 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(15),
    en => cke,
    a => x3_15);
  latch63 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(15),
    en => cke,
    a => x4_15);
  latch79 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(15),
    en => cke,
    a => x5_15);
  latch95 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(15),
    en => cke,
    a => x6_15);
  latch111 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(15),
    en => cke,
    a => x7_15);
  latch127 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(15),
    en => cke,
    a => x8_15);
  latch143 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(15),
    en => cke,
    a => x9_15);
  latch159 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(15),
    en => cke,
    a => x10_15);
  latch175 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(15),
    en => cke,
    a => x11_15);
  latch191 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(15),
    en => cke,
    a => x12_15);
  latch207 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o1(15),
    en => cke,
    a => x13_15);
  latch223 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o2(15),
    en => cke,
    a => x14_15);
  latch239 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o3(15),
    en => cke,
    a => x15_15);
  latch255 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o4(15),
    en => cke,
    a => x16_15);
  latch271 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o5(15),
    en => cke,
    a => x17_15);
  latch287 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => o6(15),
    en => cke,
    a => x18_15);

end VST;
@


1.1.1.1
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