head	1.3;
access;
symbols
	rel_1_1:1.3
	rel_1_0:1.2
	rel_0_6_1_beta:1.2
	rel_0_6__beta:1.2
	rel_0_6_beta:1.2
	rel_0_5_beta:1.1
	rel_0_4_beta:1.1
	rel_0_3_beta:1.1
	rel_0_2_beta:1.1
	rel_0_1_beta:1.1;
locks; strict;
comment	@# @;


1.3
date	2008.04.29.21.19.21;	author arniml;	state Exp;
branches;
next	1.2;
commitid	6d3481790d54567;

1.2
date	2005.06.11.10.08.43;	author arniml;	state Exp;
branches;
next	1.1;
commitid	459c42aab8184567;

1.1
date	2004.03.23.21.31.52;	author arniml;	state Exp;
branches;
next	;


desc
@@


1.3
log
@better support for ISE/XST:
opc_table and opc_decoder merged into decoder_pack and decoder
@
text
@-------------------------------------------------------------------------------
--
-- The Decoder unit.
-- It decodes the instruction opcodes and executes them.
--
-- $Id: decoder-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------

configuration t48_decoder_rtl_c0 of t48_decoder is

  for rtl

    for int_b: t48_int
      use configuration work.t48_int_rtl_c0;
    end for;

  end for;

end t48_decoder_rtl_c0;
@


1.2
log
@introduce prefix 't48_' for all packages, entities and configurations
@
text
@d6 1
a6 1
-- $Id: decoder-c.vhd,v 1.1 2004/03/23 21:31:52 arniml Exp $
a17 4
    for opc_decoder_b: t48_opc_decoder
      use configuration work.t48_opc_decoder_rtl_c0;
    end for;

@


1.1
log
@initial check-in
@
text
@d6 1
a6 1
-- $Id: decoder.vhd,v 1.39 2004/03/22 23:17:21 arnim Exp $
d14 1
a14 1
configuration decoder_rtl_c0 of decoder is
d18 2
a19 2
    for opc_decoder_b: opc_decoder
      use configuration work.opc_decoder_rtl_c0;
d22 2
a23 2
    for int_b: int
      use configuration work.int_rtl_c0;
d28 1
a28 1
end decoder_rtl_c0;
@