head	1.1;
branch	1.1.1;
access;
symbols
	arelease:1.1.1.1
	avendor:1.1.1;
locks; strict;
comment	@# @;


1.1
date	2005.04.23.00.40.58;	author tak.sugawara;	state Exp;
branches
	1.1.1.1;
next	;
commitid	1113426998c94567;

1.1.1.1
date	2005.04.23.00.40.58;	author tak.sugawara;	state Exp;
branches;
next	;
commitid	1113426998c94567;


desc
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1.1
log
@Initial revision
@
text
@# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\yacc\syn\xilinx
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = F:\yacc\syn\xilinx
SET device = xc3s200
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ft256
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Dual_Port_Block_Memory family Xilinx,_Inc. 6.1
# END Select
# BEGIN Parameters
CSET port_a_init_value=0
CSET port_b_init_pin=false
CSET port_b_enable_pin_polarity=Active_High
CSET port_a_additional_output_pipe_stages=0
CSET coefficient_file=F:\yacc\syn\xilinx\code2.coe
CSET port_b_initialization_pin_polarity=Active_High
CSET select_primitive=16kx1
CSET port_a_init_pin=false
CSET port_b_active_clock_edge=Rising_Edge_Triggered
CSET port_a_handshaking_pins=false
CSET global_init_value=0
CSET port_a_enable_pin_polarity=Active_High
CSET port_b_init_value=0
CSET depth_a=4096
CSET depth_b=4096
CSET port_a_write_enable_polarity=Active_High
CSET component_name=ram1k2
CSET disable_warning_messages=true
CSET port_a_enable_pin=false
CSET configuration_port_a=Read_And_Write
CSET write_mode_port_a=Read_After_Write
CSET configuration_port_b=Read_And_Write
CSET write_mode_port_b=Read_After_Write
CSET port_b_register_inputs=false
CSET primitive_selection=Optimize_For_Area
CSET width_a=8
CSET width_b=8
CSET port_a_active_clock_edge=Rising_Edge_Triggered
CSET port_b_additional_output_pipe_stages=0
CSET port_b_write_enable_polarity=Active_High
CSET load_init_file=true
CSET port_a_register_inputs=false
CSET port_a_initialization_pin_polarity=Active_High
CSET port_b_handshaking_pins=false
CSET port_b_enable_pin=false
# END Parameters
GENERATE


@


1.1.1.1
log
@no message
@
text
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