Hi All,
My name is Niko, I am an engineering student currently working on a Bluetooth project, namely the implementation of the BT baseband layer using an FPGA board.
While trying to write the VHDL for the receiver part, the FEC 3/2 decoder more in particular, I realised that I couldn't use the payload length indicator for generating my output valid signal, as it is itself FEC encoded. Concerning this, and also in a more general scope I wondered how in the receiving process, the end of the packet is determined, and at which stage in the process the payload length is known for sure (I think it must be after the CRC check).
If anyone could give me more insight in this, it would be great !
Thanks for reading this mail and hope to read from you.
Cheers,
Niko
Alban Villain
Inventel -
http://www.inventel.com
Paris
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