回信： [oc] (Fwd) Announcement: "Building a RISC System in an FPGA" magazi

[jimmy87@sunplus.com.tw]

Hi ALL,

After those emails about RISC in FPGA,
Personally, I think the most important thing for one RISC processor
is its ISA(instruction set architecture). If ISA is free(no patent
infringement), then anyone
could clone one RISC easily using FPGA or ASIC library.
And apply the real chip to system design worldwide.

So, at least, I think free ISA and extensively application of the chip
is the most previous feedback to the devotion of those free core
advocators and designers.

I want to say that ALL ppl use free RISC ISA, for example, OR1K,
to implement one processor and use it,
then it could then possibly reach the great goal of opencore.

Best regards,
Jimmy





"Fr嶮廨ic Renet" <f.renet@mipsys.com> 於 2000/03/16 01:43:34 AM

請回應 給 cores@opencores.org

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副本抄送： (副本密送： jimmy87/Sunplus)

主旨：    [oc] (Fwd) Announcement: "Building a RISC System in an FPGA" magazi




I think this may be of some interest for everyone.

------- Forwarded Message Follows -------
From:               "Jan Gray, Gray Research LLC" <jan@fpgacpu.org>
To:                 "Xsboard-Users" <xsboard-users@mailinglists.org>
Copies to:          <fpga-cpu@egroups.com>
Subject:            Announcement: "Building a RISC System in an FPGA" magazine
series, and XSOC/xr16 RISC SoC for XS40
Date sent:          Wed, 15 Mar 2000 12:27:23 -0500

On behalf of Gray Research LLC, I am pleased to announce that the first of
three articles in the series "Building a RISC System in an FPGA" is now on
newsstands, in the March 2000 (issue #116) of Circuit Cellar magazine.  This
series shows how to design and implement practical processors and integrated
systems-on-a-chip in small FPGAs.

In Part 1, "Tools, Instruction Set, and Datapath", we introduce the XSOC
System-on-a-Chip project and the xr16 16-bit pipelined RISC processor core,
port the LCC 4.1 retargetable C compiler, write an assembler and simulator,
and design and implement the datapath.

In Part 2, "Pipeline and Control Unit Design", we explore the processor
pipeline and design its control unit.

In Part 3, "System-on-a-Chip Design", we design and implement the on-chip
bus, memory controller, and peripherals including a bilevel VGA display.

The project was designed to be accessible to students and hobbyists.  It
fits in an XC4005XL, targets an XESS XS40 (v1.2 or later) prototyping board,
and can be rebuilt with Xilinx Student Edition 1.5.

A beta test of the accompanying XSOC Project on-line materials is now
underway.  These materials include the documentation, specifications, source
code, and schematics needed to build the XSOC Project featured in the
magazine articles.  (But they don't include the articles themselves.)

If you would like to learn more about XSOC/xr16 and/or participate in the
beta test, please visit www.fpgacpu.org/xsoc and follow the instructions.
Then let us know how it went -- write to us via the new FPGA CPU / XSOC
mailing list, fpga-cpu@egroups.com.  Future XSOC announcements will appear
there and www.fpgacpu.org.

Thank you,

Jan Gray
President, Gray Research LLC

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Fr嶮廨ic Renet
Mipsys
19c Av des Indes
91969 Les Ulis (France)
Tel: +33 1 64 86 26 00
Fax: +33 1 64 86 26 09