Re: [oc] VHDL to Verilog

["Ajit" <ajit@controlnet.co.in>]

I prefer to convert by myself ( because I didn't get the tool when wanted
:-)
You have to take care of some thumb rules in verilog code-conversions
related to blocking/Non-blocking  assignments , putting proper begin-end for
nested if-else -if loops etc etc and it is that easy.
For any verilog errors you can check it with verilint tool and for checking
whether the code conversion is proper or not you can use high end tool like
Formality from synopsys.

And thats all , you are done


Best of luck

--Ajit Madhekar
ControlNet India Pvt Ltd.
Goa, India
www.controlnetindia.com


----- Original Message -----
From: Rudolf Usselmann <rudi@inet.co.th>
To: <cores@opencores.org>
Sent: Tuesday, July 11, 2000 12:25 AM
Subject: Re: [oc] VHDL to Verilog


>
> Thanks for the pointer Ajit.
>
> I downloaded the demo, and tried it. It does not seem to run
> for me, reports some sort of error ...
>
> Anyone had more luck ?
>
> Thanks,
> rudi
>
>
>
> > I remember I have seen one on
> >
> > http://www.x-tekcorp.com/products.htm
> >
> > VHDL to Verilog and Verilog to VHDL converter.
> >
> > But never used.
> > Give a try
> >
> >
> > --Ajit Madhekar