Re: [oc] submit for IDEA processor

[MARTADINATA A <marta@vlsi.itb.ac.id>]

On Thu, 14 Sep 2000, tom st denis wrote:

> --- Rudolf Usselmann <rudi@asics.ws> wrote:
> > on 9/14/00 7:27, tom st denis at tomstdenis@yahoo.com wrote:
> > 
> > > 
> > > --- MARTADINATA A <marta@vlsi.itb.ac.id> wrote:
> > >> Hi, Damjan
> > >> 
> > >> We think we must submit our core design project about
> > >> IDEA(International
> > >> Data Encryption Algorithm) processor into the opencores main page
> > >> in
> > .....
> > >> and 
> > >> http://www.uspto.gov/patft/index.html
> > >> 
> > >> We will just use that algorithm to design a IDEA core in which We
> > >> will
> > >> make consistently its patent or copyright put on our developed
> > >> core.
> > >> We think that it is noproblem as long as for a core.
> > > 
> > > You cannot sell the core however, at any time.
> > 
> > Well, you can't build it at all ! Even if you would want to give
> > it away !
> 
> No that is wrong, Ascom has granted a non-profit license to all users
> of IDEA.  It's only if you go commercial that you have to pay for it.
> 
I agree. Because that its no problem if we just design the IDEA core.
Please give me some supports for building it and 
wait for IDEA section in opencores webpage.  
I thank all of you for advices.
> > >> The IDEA algorithm is more secret than DES algoritma because the
> > >> IDEA
> > >> secret key, 128-bit, is longer than DES key, 56-bit. And also the
> > >> IDEA
> > >> round, 8, is less than the DES round, 16. So, the IDEA processor
> > >> will be 
> > >> faster and more secret than DES.
> > > 
> > > I doubt IDEA is much faster since it requires multiplications in
> > > Z65537.  
> > 
> > Speed is a relative term. I can make any core execute in one cycle
> > at a high frequency if I pipeline it.
> > 
> > The important question here is: How many cycles of latency are
> > acceptable ?
> > 
> > Look at my DES core (www.opencores.org/cores/des). The fast
> > implementation
> > has a total of 18 pipeline stages, but can execute a crypt/encrypt
> > every
> > cycle (similar to a RISC CPU). In the current form it can run at
> > about
> > 75Mhz in a Xilinx Vertex FPGA. I could double the frequency by
> > doubling
> > the number of pipeline stages. So it could be made to run at 150Mhz,
> > but
> > would have a 36 cycle latency.
> 
> I must admit I now less about the hardware side, I just assumed that
> DES was simpler and easier todo in hardware then IDEA would be.
> 
> Tom
> 

Martadinata A.