Re: [oc] Modular FPGA Board: Block Diagram

["Yoshiaki Naruse" <sysworks@saitama-j.or.jp>]

 Sorry... but I can hardly imagine this diagram any
realistic.

Also I am very sorry to bare that I don't understand this
issue totally.     So I would appreciate ANY suggestions
to know what is going on this thread.

 It had been really tough work to satisfy required trace
length limitation of PCI specs, as you had put notices
on it.
 Although one might happen to expect there could exist some
possibility to deal with this trace-length requirement, such
like ... if he provides very low epsilon value of PCBd
material?
this had been also prohibited as the spec limits signal
speed
in a range of 150..190ps/inch.

 In PCI spec, we all know that we have to limit all signal
trace length from connecter to component within 38.1mm
with exceptions of CLK and 64-bit-specific signals.
  I understand this as very close to a [MUST] , if the
design
is not for personal use only.

 In your blockdiagram (I prefer .ps file), you had put 4
stages
of DIMM & SIMM connectors between them.   Is this really
feasible?
 When I read "PCI Hardware and Software" section 13.2,
I understand that almost nothing left free for designers.

  Or...Please advise if  I am mis-understanding you and this
issue.   Since I am assuming this as for add-in card design.

 Can I find some log file of this discussion on some Web?
 Thanks in advance.

 Best regards.

--------  Yoshiaki Naruse  --------------------