[oc] Wishbus Bus

["Winefred Washington" <wwashington@austin.rr.com>]

We may need to make an additional requirement to the Wishbone spec or
perhaps Silicore is already working on it.

I was working on a simple testbench and here's the problem I think I found.
A master device has to know what the bus width of the slave device is for
the transfer to work correctly. Suppose we have a 32-bit PCI to Wishbone
device and it has to transfer data to 32-bit  and an 8-bit devices. The PCI
core has to change how the data is presented on the bus to match the data
width of the slave devices. That means the PCI core has to contain logic
specific to the application which hurts reuse.

One solution is to fix the data widths to 32-bits for all cores.

Any comments?

Did I miss something in the spec?

WW