[oc] I'd be happy to participate and answer WISHBONE related questions.

["Wade D. Peterson" <wadep@silicore.net>]

Hello all...

I just became aware that there is a discussion going on about WISHBONE on this
reflector.  I understand that this group is evaluating WISHBONE as a SoC
interconnect, and thought I'd jump in with my two-cents worth.  Since I did most
of the work on the spec, I thought I'd make myself available for questions and
so forth.  However, I must apologize in advance if I'm not on target right away,
as I haven't been following this thread until now.

By the way - there is a Revision B WISHBONE spec in the works (it's about half
done).  Right now, these are the things that will be changing:

(1) Incorporate technical feedback from users, including: (a) additional RULEs
about WISHBONE DATASHEET (supported cycles, bus widths and clock speed
requirements); (b) clear up questions about acknowledge timing.  (2) Add a
comprehensive index in the back.  (3) Change name from 'WISHBONE Interconnection
Architecture For Portable IP Cores' to 'WISHBONE System-On-Chip (SoC)
Interconnection Architecture for Portable IP Cores'.  (4) Add 'WISHBONE
COMPATIBLE' logo.  (5) Standardize printing and covers. (6) Correct
typographical errors, change standard font to Times New Roman 12 pt, change
'WISHBONE' to all capital letters.  (7) Change steward address.  (8) Add
appendcies with application notes.  (9) Move the glossary to chapter 1.

My plan is to have this done over the next week or two.  However,  if there are
comments or suggestions for this group, then I'd be happy to incorporate them in
the next spec.

Best regards,

Wade D. Peterson
Silicore Corporation
6310 Butterworth Lane
Corcoran, MN  USA  55340
TEL: (763) 478-3567, FAX: (763) 478-3568
URL: www.silicore.net  E-MAIL: wadep@silicore.net